A central subsystem of a data processing system includes a writable control store which is loaded with firmware to control the central subsystem operations. The central subsystem logic is responsive to a sequence of commands from a system management facility to load the control store and verify that the control store firmware is loaded correctly.
A means for ascertaining the health, or basic operational status, of a system unit. A "health check" provides an indication of either "yes", the system unit is operational, or "no", the system unit is either inoperative or there is a question as to whether the system is operational. The test is performed by requesting that the system unit perform a high priority "short" operation and noting the response provided to the request; the actual execution of the request is unimportant and it is the response of the unit under test to the receipt of the request for a bus operation that is the actual indicator of the status of the unit being tested. The requested operation is not directed at the unit whose operational status is to be determined, but instead at a bus interface unit which performs bus operations for the unit to be tested and whose responses to requests for bus operations are effected by the operational status of the unit that is to be tested. The operation is not directed at an actual element in the bus interface unit, but at a phantom, or nonexistent, element.
A host computer is connected with a computer interface to a disk drive that accepts removable disk drive cartridges. A FLASH memory provides the non-volatile storage of a default embedded control program and an alternative control program for a processor. A special maintenance track on the removable cartridge is accessible by the processor and an alternative program can be uploaded from it and stored in the FLASH memory if a user interlock and the function and revision codes included in the system permit the upload. A fail-safe switch to the embedded default control program is made when problems are experienced with any uploaded program.
A controller and an associated method, which may be embodied within a disk array system, are disclosed for verifying, the integrity of command data written to a disk drive (preferably an Advanced Technology Attachment or ATA drive) before such command data is used to execute a command. The controller, which may be implemented in automated hardware or firmware residing external to the disk drive, initially writes the command data to the disk drive, and then reads back and verifies this data prior to initiating execution of the command. If the written-out and read-back command data are consistent, the controller initiates execution of the command; otherwise, the controller enters into an error state that prevents the potentially corrupt command data from being used by the disk drive. The controller may also read a status code from the disk drive more than once to reduce the likelihood of misread status information.
A data processing system has a microprocessor for executing programs useful in installing adapters having programmable option select (POS) registers. An adapter description file (ADF) stores a list of possible choices which define system resources usable by the adapter. An adapter description program (ADP) verifies certain of the choices. A configuration program then selects a valid choice and stores it in a non-volatile memory from where it can be read upon subsequent system startups into the POS registers.
Integrated circuits and methods use a margin test voltage generator that is powered at a first power supply voltage to generate a second power supply voltage that has a magnitude that is less than the magnitude of the first power supply voltage. During a low supply voltage margin test, a first logic circuit is powered at the first power supply voltage while a second logic circuit, which is the subject of the test, is powered at the second power supply voltage. As a result, the first power supply voltage may remain at a sufficient magnitude to reliably power other devices or components that are not undergoing the low supply voltage margin test.