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Claims  |
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What is claimed is:
1. Apparatus for producing a signal having a selected one of a plurality of
frequencies, each one of such plurality of frequencies being separated in
frequency one from another an amount .DELTA. f, such apparatus comprising:
(a) reference frequency oscillator means for producing a first and a second
reference frequency signals having frequencies f.sub.R1, f.sub.R2,
respectively, such frequencies being separated in frequency by the amount
.DELTA. f;
(b) second phase-lock loop means, having: a second frequency divider means,
responsive to a second control signal, for dividing a signal by a division
ratio N; and, and offset generator for producing an offset reference
frequency signal, such second phase-lock loop means being fed by the
second reference frequency signal having the frequency f.sub.R2 and the
offset reference frequency signal, for producing an output signal having a
frequency equal to the offset frequency translated by an amount
proportional to Nf.sub.R2 ;
(c) first phase-lock loop means, having a first frequency divider means,
responsive to a first control signal, for dividing a signal by a division
ratio M, such first phase-lock loop means being fed by the output of the
second phase-lock loop means and the first reference signal having the
frequency f.sub.R1, for producing a signal having a frequency equal to the
frequency of the output signal produced by the second phase-lock loop
translated by an amount proportional to Mf.sub.R1 ; and
(d) decoder means, responsive to the selected frequency for producing the
first and second control signals representative of M and N, respectively.
2. Apparatus for producing, at an output thereof, an output signal having a
selected one of a plurality of frequencies, such plurality of frequencies
being separated in frequency an amount .DELTA. f, such apparatus
comprising:
(a) reference frequency producing means for producing a pair of reference
frequency signals, a first one of the pair of produced reference frequency
signals having a frequency f.sub.R1 and a second one of the pair of
produced reference frequency signals having a frequency f.sub.R2, the
frequencies f.sub.R1 and f.sub.R2 being greater than the amount .DELTA. f;
(b) a second feedback loop means, fed by the second one of the pair of
produced reference frequency signals, for producing a second feedback loop
output signal having a frequency f.sub.os2 where f.sub.os2 is a function
of an integer multiple of the frequency f.sub.R2 ;
(c) a first feedback loop means, fed by the first one of the pair of
produced reference frequency signals and by the second feedback loop
output signal, for producing a signal having a frequency, f.sub.d,
translated in frequency from the frequency f.sub.os2 an integer multiple
of the frequency f.sub.R1, such signal being coupled to the output of the
apparatus.
3. The apparatus recited in claim 2 wherein frequencies f.sub.R1 and
f.sub.R2 are separated by an amount related to the amount .DELTA. f.
4. The apparatus recited in claim 3 wherein the frequencies f.sub.R1 and
f.sub.R2 are separated by the amount .DELTA. f.
5. The apparatus recited in claim 4 wherein the frequency f.sub.os2 is
related to an integer multiple N of the frequency f.sub.R2.
6. The apparatus recited in claim 4 wherein the frequency produced by the
apparatus is translated from the frequency f.sub.os2 an integer multiple M
of the frequency f.sub.R1.
7. The apparatus recited in claim 5 wherein the second feedback loop means
is red by an offset frequency signal of frequency f.sub.os1 and wherein
the second feedback loop output signal has a frequency f.sub.os2
translated in frequency from f.sub.os1 an amount Nf.sub.R2.
8. The apparatus recited in claim 7 wherein the first and second feedback
loop means each includes a frequency divider means for dividing by M and
N, respectively.
9. Apparatus for producing a signal having a selected one of a plurality of
frequencies, such frequencies being in a spectrum of frequencies over a
predetermined bandwith, the frequencies in such spectrum having a
predetermined frequency separation .DELTA. f, such apparatus comprising:
(a) means for producing a pair of reference frequency signals separated in
frequency by the predetermined frequency separation .DELTA. f, a first one
of such pair of reference frequency signals having a frequency f.sub.R1
and a second one of the pair of reference frequency signals having a
frequency f.sub.R2, and wherein the frequencies, f.sub.R1 and f.sub.R2 are
greater than the predetermined frequency separation .DELTA. f;
(b) means for producing a predetermined offset frequency signal, such
signal having a frequency f.sub.os1 ;
(c) a second phase-lock loop means for producing a second phase-lock loop
output signal having a frequency f.sub.os2 equal to the frequency
f.sub.os1 translated in frequency by an amount Nf.sub.R2, such second
phase-lock loop means comprising:
(i) a second mixer means, fed by the offset frequency producing means and
the second phase-lock loop output signal, for producing a second mixer
output signal having the frequency f.sub.T2 ;
(ii) a second frequency divider means, fed by the second mixer output
signal and responsive to a second control signal representing a second
integer N, for producing a signal having a frequency f.sub.N, where
f.sub.N =f.sub.T2 /N;
(iii) second loop output producing means, including second phase detector
means, responsive to the signal produced by the second frequency divider
means and the second one of the pair of reference frequency signals, for
maintaining, in a steady state condition, the frequency f.sub.N equal to
the second reference frequency f.sub.R2, for producing the second
phase-lock loop output signal with the frequency f.sub.os2 equal to the
frequency of the offset frequency f.sub.os1 translated an amount equal to
f.sub.T2 ;
(d) a first phase-lock loop means for producing the signal produced by the
apparatus having a frequency f.sub.d equal to the frequency f.sub.os2
translated in frequency an amount f.sub.T1, such first phase-lock loop
means comprising:
(i) a first mixer means, fed by the signal produced by the second
phase-lock loop means having the frequency f.sub.os2 and by the signal
produced by the apparatus, for producing a first mixer output signal
having a frequency f.sub.T1 ;
(ii) a first frequency divider means, fed by the first mixer output signal
and responsive to a first control signal representing a first integer M,
for producing a signal having a frequency f.sub.M, where f.sub.M =f.sub.T1
/M;
(iii) first loop output producing means, including first phase detector
means, responsive to the signal produced by the first frequency divider
means and the first one of the pair of reference frequency signals, for
maintaining, in a steady state condition, the frequency f.sub.M equal to
the first reference frequency f.sub.R1, for producing the apparatus output
signal having the selected one of the plurality of frequencies; and
(d) decoder means, responsive to a signal representative of the selected
one of the plurality of frequencies, for producing first and second
control signals representative of the integers M and N.
10. The apparatus recited in claim 9 wherein each of the first and the
second phase detector means produces a first and a second oscillator
signal, respectively, and wherein each one of the first and second loop
output producing means includes a voltage-controlled oscillator responsive
to a corresponding one of the first and second oscillator control signals. |
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Claims |
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Description |
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BACKGROUND OF THE INVENTION
This invention relates generally to digital frequency synthesizers and more
particularly to indirect digital frequency synthesizers adapted to produce
an output signal having a selected frequency within a band of frequencies
with predetermined frequency separation.
As is known in the art, digital frequency synthesizers generally fall into
two categories: direct frequency synthesizers and indirect frequency
synthesizers. Direct synthesizers are typically open-loop configurations
using frequency multipliers, frequency dividers, mixers and switches.
While offering the advantage of fast frequency switching and generation of
closely spaced frequencies, they are relatively hardware intensive and
have a tendency of generating an excessive number of spurious signals.
Indirect frequency synthesizers on the other hand are feedback loop
configurations adapted to produce an output signal having a selected
frequency within a spectrum of frequencies with a predetermined frequency
separation. In one type of indirect synthesizer, the feedback loop
translates a fixed offset frequency f.sub.os, which is near one end of the
operating band, by an amount (f.sub.T) required to produce an output
signal having the desired frequency, f.sub.d, i.e. f.sub.d =f.sub.os
.+-.f.sub.T. More particularly, a reference frequency signal having a
reference frequency f.sub.R is compared with a feedback signal, derived
from the output signal, having a frequency related to the actual amount of
frequency translation (f'.sub.T) provided to produce the output signal. As
a result of this comparison, an error signal is produced which drives a
voltage controlled oscillator (VCO) such that, in the steady state, the
actual amount of frequency translation provided to the output signal
(f'.sub.T) is equal to the required amount of frequency translation
(f.sub.T) to produce the desired output frequency, f.sub.d. To provide
rapid, accurate response a phase-lock loop is used for the feedback loop.
In such phase-lock loop the feedback signal is fed to a programmable
frequency divider prior to being compared with the frequency of the
reference frequency signal. The division ratio N of the frequency divider
is selected in response to a signal representative of the desired
frequency, so that N is the ratio of the required translation frequency
f.sub.T to the reference frequency f.sub.R i.e. N=f.sub.T /f.sub.R. Thus,
in the steady state, the error signal produced by a phase detector drives
the VCO so that in the steady state f.sub.d =f.sub.os .+-.Nf.sub.R
depending on whether the offset frequency is near the lower, or upper, end
of the frequency band, respectively. More particularly, the offset
frequency signal is mixed with the output signal of the phase-lock loop to
produce, in the steady state, the feedback signal having the translation
frequency f.sub.T. The frequency of the feedback signal is divided by the
integer N, selected in response to the frequency select input signal, such
that N=f.sub.T /f.sub.R. Therefore, if the desired output frequency is
f.sub.d, and assuming the offset frequency f.sub.os is below the lower end
of the spectrum, N=(f.sub.d -f.sub.os)/f.sub.R. It follows that since N is
an integer the minimum frequency separation attainable with such
synthesizer is f.sub.R, the frequency of the reference frequency signal.
An advantage of the indirect frequency synthesizer of this type s that
spurious signal levels are reduced because of the low pass filtering
action of the feedback loop. A disadvantage, however, is its longer
frequency switching time compared with the switching time of a direct
frequency synthesizer.
While such an indirect digital frequency synthesizer may be adequate in
some applications it requires that the highest operating frequency of the
programmable frequency divider generally be equal to, or greater than, the
highest translation frequency f.sub.T. However, because commercially
available digital frequency dividers have a fixed highest operating
frequency, such synthesizer may, therefore, be limited in its application.
One type of indirect digital synthesizer which reduces the required
highest operating frequency of the divider by placing the offset frequency
near the middle of the desired frequency range f.sub.d is described in
copending application Ser. No. 07/272,044, inventors Zvi Galani, Malcolm
E. Skinner, and John A. Chiesa, filed Nov. 16, 1988, and assigned to the
same assignee as the present invention.
In still another type of indirect digital frequency synthesizer, a second
phase-lock loop is provided for use in applications requiring closely
spaced frequencies without high frequency division ratios. More
specifically, a second phase-lock loop is used to synthesize a second
offset frequency f.sub.os2 used by the first, or main phase lock loop.
Such arrangement is shown in FIG. 1, where an indirect digital frequency
synthesizer 10 is shown here to produce an output signal having a
frequency within a band of 400 frequencies with a 1 MHz frequency
separation. Thus, here synthesizer 10 is shown to include a first
phase-lock loop 12. The first phase lock loop 12 (PLL1) is fed by a first
reference frequency signal having a frequency f.sub.R1, here 10 MHZ,
provided by a crystal oscillator 14 and the second offset frequency signal
on line 16 having a frequency f.sub.os2 synthesized in a manner to be
described hereinafter by a second phase-lock loop 18. The first phase-lock
loop 12 includes a phase/frequency detector 20, the output of which, after
being amplified by loop amplifier 22 and filtered by filter 24, drives a
voltage controlled oscillator (VCO) 26. The phase/frequency detector 20 is
here a model MC12040 sold by Motorola, Phoenix, Ariz. and includes
appropriate filtering at its output to produce a signal representative of
the phase between two signals fed thereto. When a first one of the fed
signals leads a second one of the fed signals, a first one of a pair of
outputs of the detector 20 produces a voltage proportional to the phase
between the two fed signals while the second one of the pair of outputs is
zero, whereas when the first one of the fed signals lags the second one of
the fed signals the first one of the outputs is zero, and the second one
of the pair of outputs produces a voltage proportional to the phase
between the two fed signals. The VCO 26 produces an output signal at
output port 28 having, in the steady state, the desired frequency f.sub.d.
A portion of the output signal is fed, via a directional coupler 30, to a
mixer 32. Also fed to mixer 32 is the second offset frequency signal
synthesized by the second phase-lock loop 18. The resulting beat
frequency, feedback signal is passed through low pass filter 34 to a
programmable frequency divider 36. The output of divider 36 is fed to the
phase/frequency detector 20, as shown. Likewise the second phase-lock loop
18 (PLL2) is fed by: a second reference frequency signal, having a
frequency f.sub.R2, here a 1 MHZ, produced by passing the 10 MHZ reference
input frequency signal produced by crystal oscillator 14 through a
frequency divider 40, here a 10:1 frequency divider; and, a first offset
frequency generator 42. The first offset frequency generator 42 produces a
signal having an output frequency f.sub.os1 either above the upper, or
below the lower end of the band of frequencies being synthesized (here
below the lower end of the band). A portion of the signal synthesized by
the second phase-lock loop 18 (for use as the second offset frequency of
the first phase-lock loop 12) is coupled to a second mixer 44 via a
directional coupler 46 along with the first offset frequency signal
produced by generator 42. Thus the beat frequency feedback signal produced
by the second mixer 44 and fed through low pass filter 48 is coupled to a
second programmable frequency divider 50. The signal produced by the
second programmable frequency divider 50 is fed to the phase/frequency
detector 52 along with the 1 MHZ second reference frequency signal
provided by the 10:1 frequency divider 40. The signal produced by the
second phase/frequency detector 52 is fed to a second VCO 54 via loop
amplifier 56 and filter 58. The signal produced by this second VCO 54 is
fed to the first mixer 32, via line 16, and to the second mixer 44 via
directional coupler 46. Completing the synthesizer 10 is a decoder 60,
here including a conventional read only memory (ROM) which, in response to
a digital word representative of the desired frequency f.sub.d to be
synthesized, produces digital commands representative of the integer
division ratios M and N for the first programmable frequency divider 36
and the second programmable frequency divider 50, respectively. It follows
then that, in the steady state, the frequency of the second offset
frequency signal produced by the second phase-lock loop 18 on line 16 will
be f.sub.os2 =f.sub.os1 +Nf.sub.R2. Therefore, in the steady state, the
frequency of the output signal at output port 28 will be f.sub.d
=f.sub.os2 +Mf.sub.R1=f.sub.os1 +Nf.sub.R2 +Mf.sub.R1=f.sub.os1
+(N)MHZ+(10M)MHZ. The data stored in the decoder 60 to generate the
desired frequency f.sub.d is presented in Table I below:
TABLE I
__________________________________________________________________________
f.sub.d = (f.sub.T + f.sub.osl) = f.sub.osl + (10M + N)MHZ
f.sub.d (MHZ)
0 1 2 3 4 5 6 7 8 9
M N M N M N M N M N M N M N M N M N M N
__________________________________________________________________________
f.sub.osl +10
-- --
1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9
f.sub.osl +20
1 10
2 " 2 " 2 " 2 " 2 " 2 " 2 " 2 " 2
"
f.sub.osl +30
2 10
3 " 3 " 3 " 3 " 3 " 3 " 3 " 3 " 3
"
f.sub.osl +40
3 " 4 " 4 " 4 " 4 " 4 " 4 " 4 " 4 " 4
"
f.sub.osl +50
4 " 5 " 5 " 5 " 5 " 5 " 5 " 5 " 5 " 5
"
f.sub.osl +60
5 " 6 " 6 " 6 " 6 " 6 " 6 " 6 " 6 " 6
"
f.sub.osl +70
6 " 7 " 7 " 7 " 7 " 7 " 7 " 7 " 7 " 7
"
f.sub.osl +80
7 " 8 " 8 " 8 " 8 " 8 " 8 " 8 " 8 " 8
"
f.sub.osl +90
8 " 9 " 9 " 9 " 9 " 9 " 9 " 9 " 9 " 9
"
f.sub.osl +100
9 " 10 " 10 " 10 " 10 " 10 " 10 " 10 " 10 " 10
"
f.sub.osl +110
10 " 11 " 11 " 11 " 11 " 11 " 11 " 11 " 11 " 11
"
f.sub.osl +120
11 " 12 " 12 " 12 " 12 " 12 " 12 " 12 " 12 " 12
"
f.sub.osl +130
12 " 13 " 13 " 13 " 13 " 13 " 13 " 13 " 13 " 13
"
f.sub.osl +140
13 " 14 " 14 " 14 " 14 " 14 " 14 " 14 " 14 " 14
"
f.sub.osl +150
14 " 15 " 15 " 15 " 15 " 15 " 15 " 15 " 15 " 15
"
f.sub.osl +160
15 " 16 " 16 " 16 " 16 " 16 " 16 " 16 " 16 " 16
"
f.sub.osl +170
16 " 17 " 17 " 17 " 17 " 17 " 17 " 17 " 17 " 17
"
f.sub.osl +180
17 " 18 " 18 " 18 " 18 " 18 " 18 " 18 " 18 " 18
"
f.sub.osl +190
18 " 19 " 19 " 19 " 19 " 19 " 19 " 19 " 19 " 19
"
f.sub.osl +200
19 " 20 " 20 " 20 " 20 " 20 " 20 " 20 " 20 " 20
"
f.sub.osl +210
20 " 21 " 21 " 21 " 21 " 21 " 21 6 21 " 21 " 21
"
f.sub.osl +220
21 " 22 " 22 " 22 " 22 " 22 " 22 " 22 " 22 " 22
"
f.sub.osl +230
22 10
23 1 23 2 23 3 23 4 23 5 23 6 23 7 23 8 23
9
f.sub.osl +240
23 " 24 " 24 " 24 " 24 " 24 " 24 " 24 " 24 " 24
"
f.sub.osl +250
24 " 25 " 25 " 25 " 25 " 25 " 25 " 25 " 25 " 25
"
f.sub.osl +260
25 " 26 " 26 " 26 " 26 " 26 " 26 " 26 " 26 " 26
"
f.sub.osl +270
26 " 27 " 27 " 27 " 27 " 27 " 27 " 27 " 27 " 27
"
f.sub.osl +280
27 " 28 " 28 " 28 " 28 " 28 " 28 " 28 " 28 " 28
"
f.sub.osl +290
28 " 29 " 29 " 29 " 29 " 29 " 29 " 29 " 29 " 29
"
f.sub.osl +300
29 " 30 " 30 " 30 " 30 " 30 " 30 " 30 " 30 " 30
"
f.sub.osl +310
30 " 31 " 31 " 31 " 31 " 31 " 31 " 31 " 31 " 31
"
f.sub.osl +320
31 " 32 " 32 " 32 " 32 " 32 " 32 " 32 " 32 " 32
"
f.sub.osl +330
32 " 33 " 33 " 33 " 33 " 33 " 33 " 33 " 33 " 33
"
f.sub.osl +340
33 " 34 " 34 " 34 " 34 " 34 " 34 " 34 " 34 " 34
"
f.sub.osl +350
34 " 35 " 35 " 35 " 35 " 35 " 35 " 35 " 35 " 35
"
f.sub.osl +360
35 " 36 " 36 " 36 " 36 " 36 " 36 " 36 " 36 " 36
"
f.sub.osl +370
36 " 37 " 37 " 37 " 37 " 37 " 37 " 37 " 37 " 37
"
f.sub.osl +380
37 " 38 " 38 " 38 " 38 " 38 " 38 " 38 " 38 " 38
"
f.sub.osl +390
38 " 39 " 39 2 39 3 39 4 39 5 39 6 39 7 39 8 39
9
f.sub.osl +400
39 10
40 1 -- --
-- --
-- --
-- --
-- --
-- --
-- -- --
--
__________________________________________________________________________
Thus, for example, if the desired frequency, f.sub.d, to be synthesized is
f.sub.os1 +235 MHZ from Table I, M=23 and N=5. From FIG. 1, it follows
that the frequency of the signal fed to the second programmable frequency
divider 50, in the steady state, will be 5 MHZ and the VCO 54 will produce
a signal having a frequency f.sub.os2 =f.sub.os1 +Nf.sub.R2 =f.sub.os1 +5
MHZ. This signal is fed via line 16 to the first phase-lock loop 12 and
hence the frequency of the signal fed to the first programmable frequency
divider 36 will be, in the steady state, Mf.sub.R1 =230 MHZ with the
result that the VCO 26 will produce an output signal having the desired
frequency f.sub.os1 +235 MHZ. Thus the pair of phase-lock loops 12, 18
translate the first offset frequency f.sub.os1 an amount f.sub.T
=Mf.sub.R1 +Nf.sub.R2 =235 MHZ. Here, the bandwidth of the translation
frequency f.sub.T is 400MHZ. Further the frequency separation is thus
equal to the frequency of the second reference frequency f.sub.R2, here
the 1 MHZ signal fed to the second phase/frequency detector 52 of the
second phase-lock loop 18. As is also known, the bandwidth of a phase-lock
loop must be substantially smaller than the frequency of the reference
frequency signal fed to such loop so that the loop provides adequate
attenuation to the reference frequency signal leaking into the loop.
Therefore, smaller frequency separation leads to narrower bandwidth
phase-lock loops with the concommitant effect of increasing frequency
switching time.
SUMMARY OF THE INVENTION
With this background of the invention in mind, it is therefore an object of
this invention to provide an improved digital frequency synthesizer.
It is another object of this invention to provide an improved indirect
digital frequency synthesize adapted to produce a signal having a selected
one of a plurality of relatively closely spaced frequencies and having a
relatively fast frequency switching time.
These and other objects of the invention are attained generally by
providing a multiple feedback loop frequency synthesizer fed by reference
frequency signals, the frequency of such reference frequency signals being
greater than the desired frequency separation provided by the synthesizer.
With such arrangement, because the bandwidth of each of the feedback loops
must be less than the frequency of the reference frequency signal fed to
such loop, achievement of frequency separation less than the frequency of
either one of the reference frequencies enables each of the feedback loops
to have increased bandwidth and hence reduced frequency switching times
and increased noise suppression.
BRIEF DESCRIPTION OF THE DRAWINGS
The foregoing features of this invention, as well as the invention itself,
may be more fully understood from the following detailed description read
together with the accompanying drawings, in which:
FIG. 1 is a block diagram of an indirect digital frequency synthesizer
according to the prior art;
FIG. 2 is a block diagram of an indirect digital frequency synthesizer
according to the invention; and
FIG. 3 is a block diagram of a indirect digital frequency synthesizer
according to an alternative embodiment of the invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring now to FIG. 2 an indirect digital frequency synthesizer 100 is
shown to include a pair of feedback loops, here phase-lock loops 102, 104,
(PLL1, PLL2), fed by a pair of reference frequency signals having
frequencies f.sub.R1 and f.sub.R2, respectively via lines 106, 108,
respectively. The digital frequency synthesizer 100 is adapted to produce
an output signal at output port 110 having a selected one of a plurality
of closely spaced frequencies within a predetermined band of frequencies;
the spacing of such frequencies being less than the frequencies f.sub.R1,
f.sub.R2 of the pair of reference frequency signals. Here the
predetermined band of frequencies extends from a frequency f.sub.os1 to
f.sub.os1 +f.sub.T and the separation in the frequencies in the band is
.DELTA. f. Thus f.sub.R1 is greater than .DELTA. f and f.sub.R2 is greater
than .DELTA. f. With such arrangement, therefore, even though the
phase-lock loops 102, 104 must have bandwidths less than the reference
frequencies f.sub.R1, f.sub.R2, respectively, fed to such loops in order
to provide adequate attenuation to the reference frequency signals leaking
into such loops, the frequency separation is here less than the frequency
of either one of the pair of reference frequency signals, and the
bandwidths of the loops are therefore sufficiently large to provide rapid
frequency switching. For example, here the first reference frequency
signal fed to the first phase-lock loop 102 via line 106 is 8 MHZ, and the
frequency of the second reference frequency signal fed to the second
phase-lock loop 104 via line 108 is 9 MHZ while the frequency separation
provided by synthesizer 100 is 1 MHZ. Thus, here the bandwidth of the
second phase-lock loop 104 (FIG. 2) would generally be 9 times greater
than the bandwidth of the prior art second phase-lock loop 18, (FIG. 1)
and hence the synthesizer 100 (FIG. 2) has faster frequency switching as
compared with the prior art synthesizer 10 (FIG. 1) even though both
synthesizers 10, 100 provide the same 1 MHZ frequency separation.
Referring now in more detail to the second phase-lock loop 104 (FIG. 2),
such loop 104 includes a mixer 112 fed by an offset frequency signal
produced by a frequency generator 114. The frequency f.sub.os1 of the
offset frequency signal is either above the upper, or below the lower end
of the band of frequencies synthesizable by loop 104, here such frequency
is below the lower end of the band. The first and second reference
frequency signals produced on lines 106, 108 are generated by a reference
frequency generator 113. More particularly, here, for example, the first
reference frequency signal, having the frequency f.sub.R1, is derived
directly from a crystal oscillator 115. The second reference frequency
signal having the frequency f.sub.R2 is derived indirectly by passing a
portion of the first reference frequency signal produced by such
oscillator 115, (having the frequency f.sub.R1) to both a mixer 116 and a
frequency divider 118. The output of the divider 118 is also fed to the
mixer 116. The frequency of the signal produced by feeding the output of
mixer 116 through a band-pass filter 120 (here a filter which passes the
upper sideband frequency) is thus f.sub.R1 +(f.sub.R1 /K)=f.sub.R2, where
K is the division integer of the divider 118. If K=f.sub.R1 /(1 MHZ),
f.sub.R2 -f.sub.R1 =the desired frequency spacing, here 1 MHZ. Thus, since
here f.sub.R1 is 8 MHZ, .DELTA. f=1 MHZ, K=8 and f.sub.R2 =9 MHZ. Thus, it
is noted that the reference frequency signals fed to both loops 102 and
104 are greater than the 1 MHZ frequency separation. The second reference
frequency signal, having the frequency f.sub.R2, here 9 MHZ, is fed to the
second phase-lock loop 104 and the 8 MHZ first reference frequency signal
produced by the crystal oscillator 115 is fed as the first reference
frequency signal for the first phase-lock loop 102. The function of the
second phase lock loop 104 is to translate the frequency f.sub.os1 of the
offset frequency signal by N f.sub.R2, where N is the division ratio of
the programmable frequency divider 122 (that is, here translate the
frequency of the offset frequency f.sub.os1 higher by Nf.sub.R2) while the
function of the first phase-lock loop 102 is to translate the frequency,
f.sub.os2, of the output of the second phase-lock loop 104 (and fed to the
first phase-lock loop 102 via line 123) an amount Mf.sub.R1, where M is
the division ratio of the programmable frequency divider 124, (that is,
here also translate such frequency f.sub.os2 higher by Mf.sub.R1). The
result is that the frequency of the signal produced at output 110, in the
steady state, will be is f.sub.d =f.sub.os1 +f.sub.T where f.sub.T =9N+8M.
The second feedback loop, here phase lock loop 104, includes a
phase/frequency detector 126 for comparing the phase of the 9 MHZ second
reference frequency signal with the phase of a 9 MHZ signal produced by
programmable divider 122. The output of the phase/frequency detector 126
is fed through a loop amplifier 128 and filter 130 to provide the control
signal for a voltage controlled oscillator (VCO) 132. A portion of the
signal produced at the output of VCO 132 is fed, via directional coupler
134, to mixer 112 and to mixer 152 of the first phase-lock loop 102. The
beat frequency signal produced by passing the output of mixer 112 through
low pass filter 136 is fed as an input to the programmable frequency
divider 122. It follows then that, in the steady state, the second
phase-lock loop 104 will track the frequency of the signal produced by the
VCO 132 to maintain it at a frequency f.sub.os1 +(9N)MHZ, where, as
mentioned above, N is the division ratio of the programmable frequency
divider 122.
Likewise the first phase-lock loop 102 includes a phase/frequency detector
140 fed, via line 106, by the first reference frequency signal produced by
the crystal oscillator 115 and by the 8 MHZ signal produced by the
programmable frequency divider 124. The output of the phase/frequency
detector 140 is fed, via amplifier 142 and filter 144, to voltage
controlled oscillator (VCO) 146. A portion of the signal produced at the
output of VCO 146 is fed, via directional coupler 150, to mixer 152 and to
output port 110. Also fed to mixer 152, via line 123, is a portion of the
signal produced by VCO 132. Thus, the beat frequency signal produced by
passing the output of mixer 152 through low pass filter 154 is fed to the
input of the programmable frequency divider 124 so that, in the steady
state, the phase-lock loop 102 maintains the frequency of the signal
produced by the VCO 146 at f.sub.d =f.sub.os1 +f.sub.T where f.sub.T
=(8M)MHZ+(9N)MHZ, and where M is the division ratio of the programmable
frequency divider 124.
Completing the frequency synthesizer 100 is a decoder 160, here including a
conventional read only memory, programmed to produce digital commands
representative of the integer division ratios M and N in response to an
applied digital word representative of the desired frequency f.sub.d. The
data stored in decoder 160 to generate the desired frequency f.sub.d is
presented in Table II below:
TABLE II
__________________________________________________________________________
f.sub.d = f.sub.osl + (8M + 9N)MHZ
f.sub.d (MHZ)
0 1 2 3 4 5 6 7 8 9
M N M N M N M N M N M N M N M N M N M N
__________________________________________________________________________
f.sub.osl +70 8 1 7 2 6 3 5 4 4 5 3 6 2 7
f.sub.osl +80
1 8 8 1 8 2 7 3 6 4 5 5 4 6 3 7 2 8 1
9
f.sub.osl +90
9 2 8 3 7 4 6 5 5 6 4 7 3 8 2 9 1 10 9
3
f.sub.osl +100
8 4 7 5 6 6 5 7 4 8 3 9 2 10
10
3 9 4 8
5
f.sub.osl +110
7 6 6 7 5 8 4 9 3 10
2 11
10
4 9 5 8 6 7
7
f.sub.osl +120
6 8 5 9 4 10
3 11
11
4 10
5 9 6 8 7 7 8 6
9
f.sub.osl +130
5 10
4 11
3 12
11
5 10
6 9 7 8 8 7 9 6 10 5
11
f.sub.osl +140
4 12
12
5 11
6 10
7 9 8 8 9 7 10
6 11
5 12 4
13
f.sub.osl +150
12
6 11
7 10
8 9 9 8 10
7 11
6 12
5 13
13
6 12
7
f.sub.osl +160
11
8 10
9 9 10
8 11
7 12
6 13
5 14
13
7 12
8 11
9
f.sub.osl +170
10
10
9 11
8 12
7 13
6 14
14
7 13
8 12
9 11
10 10
11
f.sub.osl +180
9 12
8 13
7 14
6 15
14
8 13
9 12
10
11
11
10
12 9
13
f.sub.osl +190
8 14
7 15
15
8 14
9 13
10
12
11
11
12
10
13
9 14 8
15
f.sub.osl +200
7 16
15
9 14
10
13
11
12
12
11
13
10
14
9 15
8 18 16
9
f.sub.osl +210
15
10
14
11
13
12
12
13
11
14
10
15
9 16
8 17
16
10 15
11
f.sub.osl +220
14
12
13
13
12
14
11
15
10
16
9 17
17
10
16
11
15
12 14
13
f.sub.osl +230
13
14
12
15
11
16
10
17
9 18
17
11
16
12
15
13
14
14 13
15
f.sub.osl +240
12
16
11
17
10
18
18
11
17
12
16
13
15
14
14
15
13
16 12
17
f.sub.osl +250
11
18
10
19
18
12
17
13
16
14
15
15
14
16
13
17
12
18 11
19
f.sub.osl +260
19
12
18
13
17
14
16
15
15
16
14
17
13
18
12
19
11
20 19
13
f.sub.osl +270
18
14
17
15
16
16
15
17
14
18
13
19
12
20
20
13
19
14 18
15
f.sub.osl +280
17
16
16
17
15
18
14
19
13
20
12
21
20
14
19
15
18
16 17
17
f.sub.osl +290
16
18
15
19
14
20
13
21
21
14
20
15
19
16
18
17
17
18 16
19
f.sub.osl +300
15
20
14
21
13
22
21
15
20
15
19
17
18
18
17
19
16
20 15
21
f.sub.osl +310
14
22
22
15
21
18
20
17
19
18
18
19
17
20
16
21
15
22 14
23
f.sub.osl +320
22
16
21
17
20
18
19
19
18
20
17
21
16
22
15
23
23
16 22
17
f.sub.osl +330
21
18
20
19
19
20
18
21
17
22
16
23
15
24
23
17
22
18 21
19
f.sub.osl +340
20
20
19
21
18
22
17
23
16
24
24
17
23
18
22
19
21
20 20
21
f.sub.osl +350
19
22
18
23
17
24
16
25
24
18
23
18
22
20
21
21
20
22 19
23
f.sub.osl +360
18
24
17
25
25
18
24
19
23
20
22
21
21
22
20
23
19
24 18
25
f.sub.osl +370
17
26
25
18
24
20
23
21
22
22
21
23
20
24
19
25
18
26 26
19
f.sub.osl +380
25
20
24
21
23
22
22
23
21
24
20
25
19
26
18
27
26
20 25
21
f.sub.osl +390
24
22
23
23
22
24
21
25
20
26
19
27
27
20
26
21
25
22 24
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