Logic for decreasing the number of cache lines dedicated to user data. When pools for allocation are selected using a dynamic storage allocation procedure, the size of a data block is compared to the size of the allocated pool. If the comparison results meet a predetermined criterion, the logic aligns the data to the beginning of a cache line and places the header in a separate cache line that may be deallocated. And if the data will fit within one-half of a cache slot in the allocated pool, then the line or lines having the header data can be re-used as the header is deallocated. Otherwise, user data blocks are placed in cache lines that are spatially local.

An output control method includes the step of outputting a predetermined portion of data obtained by first direct memory access as last data of one line, checking whether the data obtained by the access includes data other than the last data, performing direct memory access again with respect to data at the same address as that in the previous access as start data of a line next to the previous line when it is determined that the obtained data includes data other than the last data, and outputting a predetermined portion of the data obtained by the second access as the start data. An output control apparatus for this method is also disclosed.

A write-back cache memory and method for maintaining coherency within a write-back cache memory are disclosed. The write-back cache memory includes a number of cache lines for storing data associated with addresses within an associated memory. Each of the cache lines comprises multiple byte sets. The write-back cache memory also includes coherency indicia for identifying each byte set among the multiple byte sets within a cache line which contains data that differs from data stored in corresponding addresses within the associated memory. The write-back cache memory further includes cache control logic, which, upon replacement of a particular cache line within the write-back cache memory, writes only identified byte sets to the associated memory, such that memory accesses and bus utilization are minimized.

A computer system stores packet data and reduces the number of Read-Modify-Write (RMW) operations. An attribute is configured to specify a mode of operation that instructs the processor to perform a RMW operation, or to pad the packet data to over-write a memory line. A buffer defines the memory lines. Each memory line has a discrete number of bytes. The processor addresses the buffer with a memory address register. The attribute is a new bit in the memory address register. The attribute is configured to specify a mode of operation that instructs the processor to pad the packet data to be equal to one or more complete, full memory lines so that the padded packet data are stored only in complete, full memory lines, rather than to do an expensive RMW operation. The attribute may be a new bit added to the memory address register. A set value of the bit may indicate that a RMW operation is to be performed, and a clear value may indicate that padding of the packet data is to be done for the data to match the length of a memory line. When the data includes error correction code it is not necessary to perform a RMW, and the padding to fill a memory line is done.

A bus controller (20) for a data processing system, in which data is transferred between a bus master (10) and a bus slave (30) of a plurality of different data port sizes, is able to obtain port size information from an address signal using an incorporated address area/port size correspondence table (211), whereby a port size signal as a response signal from the bus slave is made unnecessary, thus simplifying the data processing system.