In a cache-to-memory interface, a means and method for timesharing a single bus to allow the concurrent processing of multiple misses. The multiplicity of misses can arise from a single processor if that processor has a nonblocking cache and/or does speculative prefetching, or it can arise from a multiplicity of processors in a shared-bus configuration.

A storage control apparatus contains plural request stacks for storing the access request; a stack selecting circuit for selecting a request stack by accepting the access requests one after another and for storing the access request; and a priority determining circuit for selecting the access request stored in said request stack in order of priority and makes access to a main storage unit in response to an access request from an input-output processor, instruction processor and the like. When memory access requests are issued continuously from the unit as a source of issuing the same access request to the storage control apparatus, the access request which follows can make access to a cache memory while the previous request is making access to the main storage unit, thereby preventing a reduction in a total throughput.

A cache memory system develops an optimum sequence for transferring data values between a main memory and a line buffer internal to the cache. At the end of a line transfer, the data in the line buffer is written into the cache memory as a block. Following an initial cache miss, the cache memory system monitors the sequence of data requests received for data in the line that is being read in from main memory. If the sequence being used to read in the data causes the processor to wait for a specific data value in the line, a new sequence is generated in which the specific data value is read at an earlier time in the transfer cycle. This sequence is associated with the instruction that caused the first miss and is used for subsequent misses caused by the instruction. If, in the process of handling a first miss related to a specific instruction, a second miss occurs which is caused by the same instruction but which is for data in a different line of memory, the sequence associated with the instruction is marked as an ephemeral miss. Data transferred to the line buffer in response to an ephemeral miss is not stored in the cache memory and limited to that portion of the line accessed within the line buffer.

A virtual triple ported cache operates as a true triple ported array by using a pipelined array design. Multiple execution units can access the cache during the same cycle that the cache is updated from a main memory. The pipelined features of the cache allow for three separate sequential operations to occur within a single cycle, and thus give the appearance of a virtual triple ported array. This virtual triple port array architecture contains a data interface for dual execution units, which allows both units to access the same data array location. The array architecture allows for back-to-back read accesses occurring within a half cycle. The array architecture provides a bypassing function around the array for a write occurring on one port to the same address that a read is occurring on the other port. To allow for simultaneous cache reloads during execution unit access, a late write is done at the end of the cycle.

A syncDRAM memory interface is provided that is capable of extending data burst during a data transfer in a syncDRAM memory so as to provide a continuous draw of data from the syncDRAM memory banks. Included in the interface is a pipeline request path configured to receive pipeline request data from a microprocessor, a pipeline command generator configured to generate pipeline commands and transfer them to the syncDRAM memory such that a pipeline data transfer command is transferred to the syncDRAM memory in parallel with a primary command generated from the microprocessor and sent to the syncDRAM. This pipeline data transfer command is received by the syncDRAM through the same internal address latch used in response to a primary data transfer request. A pipeline arm generator is also provided to communicate with the pipeline request path and the data transfer controller to indicate that the syncDRAM interface is ready to transfer data in response to a pipeline request.