A video graphics controller circuit for a personal computers includes a standard, EGA-compatible graphics adapter and a high-resolution companion module. A method is disclosed for configuring the graphics adapter is to generate 2 pixels in parallel in each clock cycle. The companion module serializes the pixels to generate a serial stream of pixels at twice the frequency of the graphics adapter. The companion module can also be configured as a video line driver so that the graphics controller circuit can also run software in standard video modes.
CROSS-REFERENCE TO RELATED APPLICATION
This application is a continuation-in-part of my co-pending U.S. patent application Ser. No. 056847 filed June 1, 1987, abandoned.
A PC video adapter board for driving a VGA color monitor, the board including a VGA video color palette DAC for providing analog color video to the monitor. A VGA controller provides VGA digital color video signals to the DAC through a first multiplexer and timing signals to the monitor through a second multiplexer. The board also includes EGA video controllers and a Japanese EGA (JEGA). A read/write register is written from the computer to contain additional EGA digital color bits for supplementing the six JEGA bits so as to provide a full eight bits of digital video in the EGA modes. The register provides a control bit to switch the first and second multiplexers between the VGA and EGA digital color video and timing signals. A further control bit from the register controls the third multiplexer either to send the GS and RS video signals from the JEGA directly to the first multiplexer to operate in a limited six bit mode or to send the supplementary bits to the first multiplexer to operate in an eight bit video mode. The horizontal sync and blanking signals from the EGA controllers are delayed by two pixel clock times to center EGA screens on the VGA monitor and registers in the EGA controllers are programmed to adjust the EGA snychronization timing for compatibility with the VGA monitor.
A synchronizing frequency of red (R), green (G) and blue (B) video signals is detected by a frequency detector. The resolution of the RGB video signals is calculated by a calculator. When the resolution of the RGB video signals is close to the resolution of a cathode-ray-tube (CRT), a high level signal is generated as a control signal from a control signal generator. When the high level signal is generated from the generator, the video bandwidth of the RGB video signals is limited by a video bandwidth limiting circuit to adapt the RGB video signal to characteristics of the CRT.
A graphics subsystem, including a video digital-to-analog converter, is disclosed. A high speed oscillator generates a pixel clock signal at the frequency at which pixels are to be displayed. Included in the video DAC is a frequency divider which presents an output clock signal having a period which is a multiple of the pixel clock signal, the multiple corresponding to the level of multiplexing of pixel data to be provided by the video DAC; this multiple can equal unity. The video controller in the system receives the output clock signal, and generates clock signals to control the serial port of the frame memory, and also to control the latching of the first stage in the video DAC. The first stage latch in the video DAC latches in the multiple pixel data from the frame memory, and the multiplexer in the video DAC presents the data to the color palette RAM, or around the color palette RAM in true-color non-multiplexed mode, according to the pixel clock signal. As a result, the pixel clock rate is not dependent by the propagation delay of the output clock signal through the video controller, and higher speed system operation is achieved.
A graphics subsystem, including a video digital-to-analog converter, is disclosed. A high speed oscillator generates a pixel clock signal at the frequency at which pixels are to be displayed. Included in the video DAC is a frequency divider which presents an output clock signal having a period which is a multiple of the pixel clock signal, the multiple corresponding to the level of multiplexing of pixel data to be provided by the video DAC; this multiple can equal unity. The video controller in the system receives the output clock signal, and generates clock signals to control the serial port of the frame memory, and also to control the latching of the first stage in the video DAC. The first stage latch in the video DAC latches in the multiple pixel data from the frame memory, and the multiplexer in the video DAC presents the data to the color palette RAM, or around the color palette RAM in true-color non-multiplexed mode, according to the pixel clock signal. As a result, the pixel clock rate is not dependent by the propagation delay of the output clock signal through the video controller, and higher speed system operation is achieved.
A graphics subsystem, including a video digital-to-analog converter, is disclosed. A high speed oscillator generates a pixel clock signal at the frequency at which pixels are to be displayed. Included in the video DAC is a frequency divider which presents an output clock signal having a period which is a multiple of the pixel clock signal, the multiple corresponding to the level of multiplexing of pixel data to be provided by the video DAC; this multiple can equal unity. The video controller in the system receives the output clock signal, and generates clock signals to control the serial port of the frame memory, and also to control the latching of the first stage in the video DAC. The first stage latch in the video DAC latches in the multiple pixel data from the frame memory, and the multiplexer in the video DAC presents the data to the color palette RAM, or around the color palette RAM in true-color non-multiplexed mode, according to the pixel clock signal. As a result, the pixel clock rate is not dependent by the propagation delay of the output clock signal through the video controller, and higher speed system operation is achieved.
