A method for electrically testing integrated circuits in a wafer comprises the steps of forming a layer of material (20) on the surface of the wafer having a dielectric constant which simulates the dielectric constant of the packaging material which will eventually encapsulate the integrated circuits. In one embodiment, photoresist is formed on the integrated circuit prior to wafer test. In this way, during wafer test, the capacitive coupling between the conductive structures (14) in the integrated circuit will accurately simulate the capacitive coupling between these structures after the integrated circuit is encapsulated in the packaging material.
The electrical characteristics of a semiconductor chip having a wiring layer covered with a passivation film are tested by a prober with a probe. First, part of the wiring layer, which is to be electrically connected to the probe, is selected. An opening is then formed by a laser beam in the passivation film, which corresponds to the part of the wiring layer, so as to reach down to a surface of the part of the wiring layer, and thus the part of the wiring layer is exposed. The wavelength of the laser beam is 0.7 .mu.m or less and supplied as a pulse. The depth of the opening is controlled by the number of pulses. Next the probe is inserted into the opening to bring it into electrical contact with the part of the wiring layer. In this manner, the electrical characteristics of the semiconductor chip are tested.
A function test is implemented for an individual circuit level (1) that is provided for vertical integration in a semiconductor component. Stacks of circuit levels respectively provided over or under this circuit level in the finished component are simulated as test heads (2, 3). These test heads are provided with terminal contacts for reversible contacting. The circuit level (1) under test is connected to these test heads (2, 3) during the function test, and the test heads are removed after the test.
A semiconductor probe and alignment system are disclosed. The semiconductor probe includes a silicon-based substrate and membrane on which a plurality of pyramid shaped contactors are formed. Each of the contactors includes a metalized tip for contacting bonding pads on a semiconductor die. The area of the probe surrounding each contactor is thinned to form a membrane to provide flexibility and thus compliance to assure contact between each contactor and its respective bonding pad. In the alignment system, a guide wall formed from a photo-imageable material is created around at least a portion of each bonding pad to provide alignment for guiding the contactors on the probe onto the bonding pads.
A wafer passivation structure and its method of fabrication is described. According to one embodiment of the present invention a metal layer having a bond pad spaced by a gap from a metal member is formed on a substrate. A first dielectric layer is then formed over the bond pad and the metal member and completely fills the gap. Next a second dielectric layer, having a dielectric constant greater than the first dielectric layer and being hermetic is formed over the first dielectric layer. In another embodiment of the present invention a first dielectric layer is formed on the top surface of a bond pad of a substrate. A second dielectric layer is then formed on the first dielectric. An opening is then formed through the first and second dielectric layers so as to expose the top surface of the bond pad. A barrier layer is then deposited on the sides of the opening and on the top surface of the bond pad. A contact is then formed on the barrier layer in the opening.
A wafer passivation structure and its method of fabrication is described. According to one embodiment of the present invention a metal layer having a bond pad spaced by a gap from a metal member is formed on a substrate. A first dielectric layer is then formed over the bond pad and the metal member and completely fills the gap. Next a second dielectric layer, having a dielectric constant greater than the first dielectric layer and being hermetic is formed over the first dielectric layer. In another embodiment of the present invention a first dielectric layer is formed on the top surface of a bond pad of a substrate. A second dielectric layer is then formed on the first dielectric. An opening is then formed through the first and second dielectric layers so as to expose the top surface of the bond pad. A barrier layer is then deposited on the sides of the opening and on the top surface of the bond pad. A contact is then formed on the barrier layer in the opening.
