In a timer apparatus, the clock controlling circuit thereof outputs a clock signal during a period in which an input signal is significant. The counter thereof counts the number of pulses of the clock signal to generate a count-up signal when the value of count reaches a prescribed value. The initialization circuit thereof outputs an initialization signal when the input is not significant. The clock controlling circuit stops the output of the clock signal when the count-up signal is generated. Thereby, it is prevented to misjudge the detection of an effective pulse width to achieve the effective pulse width though the pulse width of the pulse does not actually reach the effective pulse width actually.

A deglitch circuit utilizes a first flip-flop coupled to the input signal and a second flip-flop coupled to the output of a circuit with feedback from the output to gates to control first and second inputs to the first flip-flop. In an alternative arrangement, a counter is provided between the output of the first flip-flop and the input to the second flip-flop in order to provide flexibility and the possibility of a longer delay for the circuit.

A signal processing circuit and method for measuring the width of an input pulse signal that contains chattering noise. The signal processing circuit converts the input pulse signal into an output pulse signal having no chattering noise by setting and resetting a flip-flop circuit at a timing that is delayed by a predetermined time after the rise and fall in the input pulse signal.

In a pulse filtering device, the pulse signal is sampled to enable the counting of this signal by an asynchronous counter. A pulse of calibrated duration is generated when the counting reaches a predetermined number.

A noise eliminating circuit for identifying and eliminating a noise component from an input signal and obtaining a normal signal as its output signal comprises first and second detectors and an output determining section. The first detector continuously monitors the logic level of the input signal by at least one first detecting element for detecting that the inut signal is at a first logic level and detects that the input signal has the first logic level within a predetermined operating cycle, every the operating cycle. The second detector continuously monitors the logic level of the input signal by at least one second detecting element for detecting that the input signal is at a second logic level and detects that the input signal has the second logic level value within the predetermined operating cycle, every the operating cycle. The output determining section determines its output signal such that the output signal is made at the first logic level in a first case where only the first detector continues its detection over a predetermined time period, the output signal is made at the second logic level in a second case where only the second detector continues its detection over the predetermined time period, and the output signal is held at the logic level that it had previously in other cases than the first and second cases.