Apparatus for determining priority of access to a bus by nodes in a group of nodes attached to the bus. For purposes of determining priority, the apparatus arranges the nodes in a circular configuration and selects one of the nodes as the "anchor node". The anchor node has the highest priority and the priorities of the other nodes are determined by their positions in the circle relative to the anchor node. Each time a device represented by one of the nodes accesses the bus, the current anchor node ceases being the anchor node and the next node in the circle becomes the new anchor node. The priorities of the nodes change to reflect the new location of the anchor node.
CROSS REFERENCES TO RELATED APPLICATIONS
This is a continuation of co-pending application Ser. No. 097,775, filed on Sept. 17, 1987, now abandoned, which is a continuation-in-part of Ser. No. 712,492, filed Mar. 15, 1985, now U.S. Pat. No. 4,719,622.
An inter-processor communication system for a multi-processor environment wherein each processor has an associated processor system controller comprising an inter-processor communication registers (IPC Comm Reg). The IPC Comm Reg further comprising a response command register (CMD1 Reg), a non-response command register (CMD2 Reg), and a response register (RSP Reg). During inter-processor communication, the IPC Comm Reg of an initiating processor is coupled to the IPC Comm Reg of a target processor via the IPC bus so that data can be transmitted and one or more of a set of control flags of the target IPC Comm Reg is cleared or set in response to a write or read operation. In the inter-processor communication method for communication between multiple processors the initiating processor system controller coupled to an initiating processor detects the state of a set of status control flags of an initiating IPC Comm Reg associated with that initiating processor. In response to the detected state of the set of status control flags, the initiating system controller writes data to a remote target IPC Comm Reg of a remote target processor system controller, and also sets an associated interrupt flag in the target IPC Comm Reg in response to that write operation. The target system controller then detects the set interrupt flag in the target IPC Comm Reg, and in response thereto, reads data from the target IPC Comm Reg. Moreover, the initiating and/or target system controller may perform additional command sequence depending on the communication mode selected, i.e., auto-response method, CPU-response method, or non-response method.
A transfer request bus (25) is described which is suitable for use in a data transfer controller processing, multiple concurrent transfer requests despite the attendant collisions which result when conflicting transfer requests occur. Transfer requests are passed from an upstream transfer request node (318) to downstream transfer request node (300) and thence to a transfer request controller with queue (320). At each node a local transfer request can also be inserted to be passed on to the transfer controller queue. Collisions at each transfer request node are resolved using a token passing scheme wherein a transfer request node possessing the token allows a local request to be inserted in preference to the upstream request.
A method and apparatus for early arbitration in a full duplex bus system. Early arbitration in a distributed arbitration serial bus system permits the resolution of requests for a next fairness interval during a current fairness interval such that the grant of the highest priority request in the next fairness interval may immediately follow a last packet of a last subaction in a current fairness interval. In this way, the bandwidth previously wasted propagating an arbitration reset token and waiting for arbitration requests can be substantially eliminated.
A communication system includes a plurality of communication stations communicating with each other over a communication channel, wherein each station is provided with a station number which is transmitted as part of a data signal. Transmission control circuitry in each station detects the presence of a carrier wave on the communication channel indicating that another station is transmitting data. The station number is read from the transmitted data and is used to determine the length of a waiting period during which no carrier wave is detected, and after which the station can transmit data. Data collision circuitry is provided which causes data retransmission in the event of a data collision on said channel, after a waiting period determined by the station number of the transmitting station.
A priority decision circuit decides priorities of a plurality of slots on the basis of access frequencies or the like. In conformity with these priorities, a bus mapping circuit performs mapping allowing a slot having a higher priority to be connected to the upper hierarchical bus whereas it performs mapping allowing a slot having a lower priority to be connected to the lower hierarchical bus.
