A multiprocessing system includes a cache coherency technique that ensures that every access to a line of data is the most up-to-date copy of that line without storing cache coherency status bits in a global memory and any reference thereto. An operand cache includes a first directory which directly, on a one-to-one basis maps a range of physical address bits into a first section of the operand cache storage. An associative directory multiply maps physical addresses outside of the range into a second section of the operand cache storage section. All stack frames of user programs to be executed on the time-shared basis are stored in the first section, so cache misses due to stack operations are avoided. An instruction cache haivng various categories of instructions stores a group of status bits identifying the instruction category with each instruction. When a context switch occures, only instructions of the category least likely to be used in the near future are cleared decreasing delays due to clearing of the instruction cache as a result of context switches. A page-mapped I/O cache structure interfaces by a large number of I/O channels which regard a single I/O cache as an exclusive buffer. System operating delays due to maintaining cache coherency, operand cache misses, instruction cache misses, I/O cache misses, and maintaining a cache coherency are substantially reduced.
CROSS REFERENCE TO RELATED APPLICATION
This application is a continuation-in-part of copending patent application Ser. No. 07/236,449, "COHERENT CACHE STRUCTURES AND METHODS", by Daniel M. McCarthy, Joseph C. Circello, Gabriel R. Munguia, and Nicholas J. Richardson, filed on Aug. 25, 1988, assigned to Edge Computer Corporation. See also copending Ser. No. 07/236,646, "PIPELINE STRUCTURES AND METHODS" by Joseph C. Circello, Richard H. Duerden, Roger W. Luce, and Ralph H. Olson, filed on Aug. 25, 1988, assigned to Edge Computer Corporation, and incorporated herein by reference.
The invention comprises a system bus apparatus and method for a multi-arm, multiprocessor computer system having a main memory and localized buffer cache memories at each processor. Each block of data in a cache includes tag bits which identifies the condition of the data block in relation to the corresponding data in main memory and other caches. The system bus (SYSBUS) comprises three subparts; 1) a MESSAGE/DATA bus, 2) a REQUEST/GRANT bus and 3) a BCU bus. The MESSAGE/DATA bus is coupled to every device on the system and is used for transferring messages, data and addresses. The REQUEST/GRANT bus couples between every device on an arm of the system and that arm's bus control unit (BCU). The BCU bus couples between the various BCUs. Both the MESSAGE/DATA bus and the BCU bus include ACK/NACK/HIT bits which are used when responding to messages received over the SYSBUS to inform the message-issuing device if the devices received the message and, if so, the condition of the data in relation to other caches and main memory. The protocol allows inconsistent copies of data to exist and prevents stale data from being used erroneously by monitoring the tag bits and the ACK/NACK/HIT bits. Further, under the appropriate conditions, a copy of the most recent data block may be transferred from one cache to another (with appropriate updating of tags) without updating the main memory. When a memory operation will bring about a situation where cache coherence can no longer be maintained, main memory is updated with the most recent copy of the data and the other caches are either updated or tagged as invalid.
A distributed file system controls memory allocation between a global cache shared storage memory unit and a plurality of local cache memory units by calculating a variable global cache LRU stack update interval. A new update interval is calculated using fresh system statistics at the end of each update interval. A stack update command is issued at the end of the update interval only if the expected minimum data residency time in the global cache shared memory is less than or equal to the expected average residency time in the local cache memory.
A hierarchical cache memory apparatus assembled in a multiprocessor computer system including a plurality of processors and a memory device, includes a plurality of first cache memory devices arranged in correspondence with the plurality of processors and each including a controller including a first status identification section for identifying status of each of a plurality of pieces of address information, a plurality of first connection devices for connecting the plurality of first cache memory devices in units of a predetermined number of devices to constitute a plurality of mini-cluster devices a plurality of second cache memory devices respectively connected to the first connection devices in correspondence with the plurality of mini-cluster devices, having all the addresses of address information of the plurality of first cache memory devices in the mini-cluster devices, and each comprising a controller including a second status identification section for identifying status of each of the plurality of address information, and a memory device connected to the second connection devices and having all the addresses of the plurality of address information of the plurality of second cache memory devices.
An information processing apparatus is constructed to include a judging part for decoding an address of an input request and outputting a judgement signal which indicates whether the input request is a cache control request or a DMA control request, and a control part for carrying out a cache control when the judgement signal from the judging part indicates the cache control request, and carrying out a DMA control when the judgement signal indicates the DMA control request.
A lock control for a data processing system providing lock control for each data processing unit in the data processing system. The lock control is carried out based on a state of a lock variable, by a lock request control unit of a cache unit connected to the data processing unit. On receipt of a lock request or unlock request, the lock request control unit indexes a lock address register holding an address of the lock variable and refers to a state of a lock stored in a corresponding lock status register. Various kinds of states are defined as a state of a lock variable to indicate that each lock request control unit is in a lock or unlock state. A symbol ULE indicates the state that no acquisition of a lock in all lock request control units is confirmed. Thus, an acquisition of a lock corresponding to a particular lock request control unit can be done with high speed, without confirming states of lock request control units other than the particular lock request control unit.
