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Description  |
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The invention pertains generally to systems for the acquisition of analog
data by digital processors and is more particularly directed to such
systems which include many high speed data acquisition channels.
The acquisition of analog data by a digital processor is known to include
the conversion of an analog signal to a digital form by an analog to
digital converter and the input of the converted digital value by the
processor over a data bus. The data in digital form, once stored in the
processor memory, can be further processed and used for a variety of
purposes. Software process control systems based upon the digital
conversion and input of sensed analog values are common. Other systems use
converted analog data for diagnostic purposes where the values pertain to
limits or alarm values. Another of the more advantageous uses for such
systems is to collect data relating to a physical event from a
multiplicity of the sensors for later analysis.
Systems for the collection of physical data and its digitization and
storage are prevalent in scientific systems where vast quantities of data
need to be analyzed. Examples of such disciplines where these systems have
been used to advantage are physics, astronomy, medicine, chemistry and
others. Physical event data acquistion systems generally present the
problem of simultaneously digitizing many data channels and efficiently
recording the outputs of the channels from which the individual data was
taken.
A specific example of an advantageous use of this type of data acquisition
system would be in connection with a barrel-shaped electromagnetic
calorimeter termed the High-Density Projection Chamber (HPC). The HPC is a
fine grained gas sampling calorimeter which uses the principle of time
projection to obtain a three-dimensional localization of the energy
deposition within it. A series of proportional tubes with U-shaped cross
sections are used to amplify the drifted charge and the signals induced on
the cathodes of these tubes are collected on a series of pads. The HPC
includes 128 readout pads in each of 144 sectors, for a total of 18,432
readout channels.
This calorimeter can be utilized to measure the charge deposited by
photons, electrons or other charged particles passing through it. An
interesting physical experiment in which charged particles are generated
for basic elementary particle research will be performed at the Large
Electron Positron Collider, in which two charged particle beams are
collided to radiate a number of other smaller charged particles. These
emitted particles can then be detected by measuring the energy which they
impart to the gases of the barrel calorimeter upon impingement.
However, in order to resolve the energy of single photons and pions, the
calorimeter in such instances would have to sample the collected charge
256 times per event over the 90 cm. drift length of each calorimeter
sector. This necessitates the collection of digitized charge information
for approximately 4.7 X 10.sup.6 spatial samples per event. Moreover, the
beam crossing rate of the collider requires that digitization of the
charge deposited by the particles traversing the calorimeter occur at a
frequency of about 15 MHz. Additionally, the charge deposited by
individual pions and electrons is relatively small with respect to groups
or showers of particles. In order to provide for the sampling of minimum
ionizing particles and showers of energies 20 GeV without appreciable
saturation, a dynamic range of approximately 800:1 is needed. Therefore,
the data acquisition system for such configuration must convert massive
amounts of analog information to a digital format in a very short time and
over a large dynamic range.
In scientific digitization systems generally, and particularly in the HPC
example, there is, much of the time, no relevant data present in many of
the data samples. Such digitizations of irrelevant values, or even zero
values, take up memory space, and they should be discarded. However, the
time constraints of data acquisition for a large number of channels for
such systems make such further data processing difficult to accomplish
concurrently.
The calibration of data acquisition systems with a large number of data
channels further presents difficulty. The gains and zero values for each
channel must be set before the digitization system can take an accurate
measurement. With a large number of data channels, a manual calibration,
or even an automated calibration, can take a significant amount of time.
Another difficulty encountered with the digitization of data from a large
number of data channels is the efficient transfer of the data from the
acquisition system to a host processor. When massive amounts of data must
be moved from one system to another, an efficient communications interface
must be used. Otherwise, the acquisition system will spend more time
transferring the data than acquiring it. A method of providing efficient
data transfer for digital systems is to make the transfer hierarchial
where data can be preprocessed before transfer o to the host.
Preprocessing can further be accelerated by distributing the processing
engines, either serially or in parallel. An efficient communications
interface which can be used to connect a host processor with a large
number of peripheral devices is the FASTBUS. This bus, which implements
IEEE Standard 960-1986 for communications, is a 32-bit wide gateway for
data and information between a host and its peripherals. However, this
efficient communications interface has not been used in a data acquisition
system utilizing a distributed and/or hierarchial preprocessing data
transfer technique.
SUMMARY OF THE INVENTION
The invention solves these and other problems of data acquisition systems
by providing a system which efficiently digitizes information from a
multiplicity of channels and transfers it to a host processor.
In a preferred embodiment, a data acquisition system includes a plurality
of data acquisition modules, each adapted to digitize the analog
information from a multiplicity of input channels. Each module includes a
communications coupler which interfaces with an efficient communications
structure for transferring data to a host processor. In the implementation
illustrated, the communications coupler connects each module to a FASTBUS
backplane which is then interfaced to the host processor.
Each data acquisition module comprises, in addition to the communications
coupler, a multiplicity of input digitization circuits including a flash
analog to digital o converter (FADC), a cache memory for buffering
converted information, and means for reading data from said cache circuit
onto a submodule bus. The modules are triggered by the host to convert a
plurality of sequential time slots (event) into digital samples which are
then stored to the cache memories.
Each submodule bus connects the cache memories of a plurality of the input
channels to a front end buffer (FEB). Between the FEB and each cache is a
zero suppression circuit which filters the data for non-zero o values.
Because only non-zero values of the data are passed from each cache memory
to a FEB, each FEB is divided into two sections where one section stores
the data samples and another section stores a digital value corresponding
to a time slot at which the data was taken.
The zero suppression circuit, including an address generator, will reject
data values based on a threshold values are clocked sequentially out of
each cache memory, and the address generator determines whether the data
is retained. The selection is made by first clocking
data into the FEB at an address generated by the address generator and then
retaining the data by incrementing the address or discarding the data by
overwriting depending on whether it passes the zero suppression criteria.
The zero suppression criteria, in the preferred implementation, threshold
and width, are stored in a random access memory which can be read and
written to change the parameters stored therein.
In the preferred embodiment, zero suppression is effected if a data sample
does not exceed a threshold, which in turn exceeds a pedestal level. The
pedestal levels are determined from the zero values of each FADC of the
module during a calibration operation. If the data sample is above the
threshold, it will be tentatively stored until it is determined if the
subsequent two samples are above the threshold thereby passing the width
test.
The FEB is further partitioned into individual memory spaces for each
associated channel which can hold multiple events for that channel. The
partitioning is such that each event begins at a fixed location in the
FEB. The lower order byte at this location contains the valid word count
for the channel, i.e., the number of data words corresponding to non-zero
data values.
Each module further comprises a module bus and a local processor with
random access memory which is further connected to the module bus. The
module thus exists as a pathway between the FEB of each submodule, the
local processor, the module event buffer memory, threshold and width
memories, and the communications coupler. The FEB, threshold and width
memories, and the module event buffer exist in the memory space of both
the local processor and the communications host.
This architecture provides an advantageous method for transferring
digitized data to the communications host. In a first method, the
communications host can directly access and upload from the FEB of each
submodule of each module. Alternatively, the local microprocessor can
upload the data o from each submodule to the event buffer and the
communications host can upload each event buffer from each module.
This method is advantageous in that the local processors of each module
work in parallel to process the data from the FEBs to a single place in
each module event buffer where more effective block transfers of data are
possible. The local processor also works in series with the zero
suppression processor to provide a hierarchial processing technique. In
addition, the local processor is capable of reformatting the data from FEB
format to a format compatible with the communications host. Moreover, the
system with the local processor is capable of additional data compression
and analysis or other front end processing on the FEB data. The amount of
processing by the local processor is variable to the degree needed for a
particular application. Any number of different programs can be provided,
since the local processor program is downloaded into the module memory
before the beginning of data collection.
According to another feature of the invention, each local processor can
auto-calibrate the FADC channels associated with its module. The local
processor performs the calibration by executing a calibration program
downloaded from the communications host. The calibration program disables
the zero suppression and averages a number of data samples taken during a
quiescent event time of the device. From these samples, the local
processor computes a pedestal level for each channel under its control.
Since all the local processors operate in parallel, a calibration which
otherwise would be laborious and time consuming can be accomplished with
facility.
These and other objects, features, and aspects of the invention will become
apparent and more fully described upon reading the following detailed
description when taken in conjunction with the attached drawings wherein:
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a system block diagram of an apparatus for measuring a physical
event incorporating a data acquisition system constructed in accordance
with the invention;
FIG. 2 is a detailed block diagram of one of the segments of the event
generator illustrated in FIG. 1 showing the module groupings associated
therewith;
FIG. 3 is a detailed functional diagram of one of the data acquisition
modules of the data acquisition system illustrated in FIGS. 1 and 2;
FIG. 4 is a detailed hardware block diagram of the module bus, local
processor, the FASTBUS coupler, and their interconnections;
FIG. 5 is a detailed block diagram of the timing and control circuitry
associated with the module illustrated in FIG. 3;
FIG. 6 is a pictorial representation of various timing and clock signals
generated by the circuitry illustrated in FIG. 5;
FIG. 6A is a schematic of the watch dog driver of the system;
FIG. 7 is a detailed electrical schematic of the input channel circuitry
illustrated in FIG. 3;
FIG. 8 is a detailed electrical schematic diagram of the circuitry to
generate the plurality of reference voltages which are used by the FADC
illustrated in FIG. 7:
FIG. 9 is a detailed electrical schematic diagram of the FEB of one
submodule illustrated in FIG. 3;
FIG. 10 is a pictorial representation of the allocation of memory space in
a FEB of one submodule illustrated in FIG. 3;
FIG. 11 is a pictorial representative of the allocation of memory space for
the threshold and width memories of the module illustrated in FIG. 3;
FIG. 12 is a detailed electrical schematic diagram of the control circuitry
for the FEB memory and the threshold and width memories of the module
illustrated in FIG. 3;
FIG. 13 is an electrical schematic diagram of the threshold and width
memories, and address generators which form the zero-suppression circuitry
of the module illustrated in FIG. 3;
FIG. 14 is a detailed electrical schematic diagram of one of the address
generators illustrated in FIG. 13;
FIG. 15 is a pictorial representation of various data samples being
compared by the zero suppression circuitry;
FIG. 16 is a detailed electrical schematic of the local processor, control
interface, arbitration logic, control status register, and interrupt
control illustrated in FIG. 4;
FIG. 17 is a detailed electrical schematic of the module memory, cross
connect, and memory control illustrated in FIG. 4;
FIG. 18 is a detailed block diagram of the FASTBUS coupler illustrated in
FIG. 4;
FIG. 19 is a pictorial representation of timing waveforms representing a
communication between the FASTBUS backplane and the FASTBUS coupler
illustrated in FIG. 18;
FIG. 20 is a system flow chart of the executive program for controlling the
data acquisition system illustrated in FIG. 1;
FIG. 21 is a detailed flow chart of the initialization routine illustrated
in FIG. 20;
FIG. 22 is a detailed system flow chart of a threshold calibration
operation;
FIG. 23 is a detailed system flow chart of a gain computation operation;
and
FIG. 24 is a pictorial representation of a reformatted data blocklet sent
to the host by the local processor.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
FIG. 1 illustrates a system for the acquisition of digital data related to
a particular physical event which includes a data acquisition system
constructed in accordance with the invention. The system includes an event
generator 10 which is a device equipped with a multiplicity of sensors to
take measurements of a physical phenomena. As an example, the
specification will use as an event generator the barrel calorimeter
described for the HPC. While data acquisition for this particular
phenomena requires a multiplicity of data sensors, there are many other
event generators which are equivalent in that they require many sensors
operating simultaneously to record an event properly.
In the system illustrated in FIG. 1, the event generator 10 comprises six
segments 1-6, each having 24 sectors, for a total of 144 sectors. Each
sector 1-144 has multiple data sensors shown schematically at 13, 15, 17,
19, 21 and 23 which connect to groups of segment modules 12, 14, 16, 18,
20 and 22, respectively. The segment modules contain a plurality of
modules for each sector and segment, such that sufficient circuitry is L
provided to digitize all the analog signals detected by the sensors. The
segment modules 12-22 connect to a communications bus 25 which transfers
the recorded digital data from the sensing of an event to a communications
host 26 through an interface 24. In the preferred embodiment, this
communications bus 25 is a master/slave driven communications interface
termed a FASTBUS. The segment modules 12-22 are identical such that they
interconnect easily to the FASTBUS backplane 25.
The communications host 26 is under a control of a system host 28 to input
and process the data which is measured by the data acquisition system 27.
The system host 28 communicates to the data acquisition system 27 via the
communications host 26 and the interface 24. An event control 30 further
communicates to the system host 28 through communications host 26. The
event control 30 provides timing and clock lines 32 to the segment modules
12-22. The event control 30 further has sensors 35 which are read on lines
34 which do not take data but are for event control and processing of the
data acquired during an event.
In operation, the sensors 35 attached to sensor lines 34 detect particular
parameters and cues concerning the physical status of the event generator
10 and cause the event control 30 to issue a trigger to begin the data
acquisition by data acquisition system 25. The data acquisition system 25
digitizes the inputs from the multiplicity of sensors 13-23 and then
transfers this acquired data either in full or compressed form via the
FASTBUS backplane 25 to the communications host 26 and eventually the
system host 28.
If, durinq the digitization, the event control 30 determines that the
detected event is not interesting, then it can reset the data acquisition
system 27. Thus, the system will only digitize during events (triggers)
and only for the amount of time necessary to determine the event may have
significant data. If there is a determination that the data is interesting
then it will be stored and further processed. The segment modules 12-22
will communicate to the communications host 26 whether significant data is
stored or not.
A more expanded view of the modules which comprise one segment group, for
example segment group 12, is shown in FIG. 2. Each segment module group
contains 24 sector groups of which sector 1 at 40 is an example. Sectors
2-24 are represented as sector modules 50-62, respectively, and contain
the same configuration and number of modules that sector 1 at 40 contains.
The sector 1 group comprises four modules 42, 44, 46 and 48, each of which
are coupled to the FASTBUS backplane 25 and to a plurality of sensors 39
for the respective sector of a segment. In a preferred embodiment, each
module, for example 42, digitizes the inputs from thirty-two channels
0-31. The total system, thus, instruments 128 channels for each of the 144
sector groups for a total of 18,432 channels. Because of the particular
event generator 10 described, 256 time slots are measured per event. Total
digitized information for the system of approximately 4.7 x 10.sup.6 data
words are thereby recorded per event. Such massive data acquisition in a
relatively short period of time requires the efficient and extremely fast
data acquisition system which is provided by the invention.
With respect now to FIG. 3, there is shown a detailed block diagram of one
module, for example the one designated 42 in FIG.2, of the multi-channel
data acquisition system. The module 42 comprises a plurality of submodules
66, 68, 70, and 72 connected to a module bus 77. Each of the submodules,
for example 66, includes a plurality of input channel circuits comprising
an input channel group (for example, channel group 80) a zero suppression
circuit 82, a FEB (FEB) 84, and gates 86, 88. Each of the input channel
circuits of a channel group 80 includes an input amplifier 92, a flash
analog to digital converter (FADC) 94, a cache memory 96 and a gate 98.
The module further includes a local processor 104 connected to the module
bus 77 and associated module memory 106 similarly connected to the module
102 bus. Completing the elements of the module 42 is a communications
coupler 102 coupling the module bus 77 to the FASTBUS backplane 25.
In operation, the analog signal from the respective event sensor is input
to the amplifier 92, differentially amplified, and then converted to a
digital value by FADC 24 at a specified clock rate. The digital values are
temporarily stored in the cache memory 96 of the input channel circuit
until an entire event is recorded (256 samples). When the loading cycle is
complete, the data is transferred (dumped) to the FEB 84 from each cache
memory of the eight channels in the group. The unloading of the cache
memories for a group 80 is sequential, with the first finishing before the
next starts. Gate 86 which is closed for the load cycle is open during the
dump cycle and is connected to the open gate of group 80 in sequence. The
data flows first to the zero suppression circuit 82 which causes data
values below a threshold and less than a predetermined width to be
discarded.
After data from the cache memories of the associated channel groups have
been transferred to the FEBs of the submodules 66, 68, 70 and 72, one of
two operations may take place to upload the data to the communications
host 26. The first operation includes the direct addressing of the FEBs by
the communications host 26 to take the information directly. The
communications host 26 accomplishes the transfer by enabling gate 88 of a
submodule, and by then addressing the FEB 84 directly.
Alternatively, and more advantageously, the local processor 104 controls
the transfer the information stored in each FEB for each submodule into
the section of module memory 106 designated as the module event buffer
100. The communications host 26 can then perform a block transfer of all
the data for a module by addressing the module event buffer 100. The local
processor 104 is halted during the load and dump cycles of the submodules
so that it Will not interfere with the sensitive analog sensors of the
design.
In the preferred implementation shown in the drawing, the module 42 is
capable of digitizing 32 channels of information, CHAN0-31. These 32
channels are partitioned into groups of 8 input channel circuits, where
each group shares a zero suppression circuit and a FEB. While each group
shares a zero suppression circuit, there is provision for each input
channel to have its own suppression criteria. A group of 8 input channels,
a zero suppression circuit and a FEB form one of the four submodules. The
four submodules, the module event memory 106, the local processor 104, the
module bus 77 and the communications coupler 102, comprise the module 42.
A more detailed block diagram of the local processor 104 and the module bus
77 are shown to advantage in FIG. 4. The module bus 77 comprises a control
bus 108, a 19-bit wide address bus 110, and a 32-bit wide bidirectional
data bus having data lines D0-D15 and data lines D16-D31 at 112. The
module bus 77 is common to the local processor 104, the communications
coupler 102 and the module memory 106 thereby allowing access of the
module memory by either the local processor or the communications host
through the coupler 102.
The system further includes arbitration logic 114 to determine which
processor, the local processor 104 or host processor, will control the bus
77, for how long and by what protocol. A control interface 56 also
generates control signals which assist the local processor and the
communications coupler to handle the module bus 77. In addition, the
control interface provides control signals to a cross-connect circuit 60
to allow the data on line D0-D15 of the data bus to be applied to the
opposite data lines D15-D31, and vice versa. A control status register
CS10 at 118 is selected by control lines from the address bus 110 to
select the module. Once selected, the control status register CSR10 inputs
data from the communications coupler via the data bus 112. These data are
the control commands of the communications host for the local processor
104. The commands of the control status register 118 are translated by an
interrupt control 120 into interrupts which command a microprocessor 122
to transfer command processing to selected control routines. The memory
control 124 is accessible by both the local processor 104 and the
communications host 26 to either read or write data into the module memory
106.
Because the communications coupler 102 uses a 32-bit data bus and the
microprocessor 122 uses a 16-bit data bus, it is necessary to reconfigure
the data bus 112 dynamically from 32 to 16 bits. This is done by a
cross-connect circuit 128 which connects data lines D16-D31 to their
corresponding data lines D0-D15 when the microprocessor 122 tries to
access data that would be in the upper 16 bits in a 32-bit word. The
control signals provided by the communications coupler 102 are not the
same as those recognized by the microprocessor 122 and module memory 106.
Therefore, control interface circuitry 126 is provided to transform the
signals from the FASTBUS coupler 102 into compatible signals.
The system has a series of triggers or levels which causes data from
individual events to be accepted for further processing or discarded as
not of current interest. These trigger levels provide a prefilter or
preprocessor for the massive amounts of data which the system is able to
digitize. The system is presently configured to be capable of digitizing
18,432 sensor output channels, each having 256 samples, every 22
microseconds. If all of this data were stored even for a short time, the
processing capabilities and storage of the host would be overextended.
Because, in many physical experiments, much of the data is not
interesting, as it does not include the event being searched for,
extraneous values should be discarded at the earliest possible time in the
system processing cycle so as not to tie up higher level system assets.
Therefore, at a first level, the system is triggered to begin taking data
for an event. In the present example, this trigger is coincident with the
beam crossing of two particle beams which produces charges in the
calorimeter. No trigger is applied to the system unless there is a good
possibility that significant data will result, i.e., a prescreened event
occurs. If during the digitization of an event or the buffering of the
data in the FEBs, the event control 30 decides that the event data should
not be further processed, then a second level trigger will reset the
system. The transfer of the digitized data will not be made, but the
system will instead cycle back to an idle mode and be immediately ready to
digitize another event upon synchronization with the next beam crossing.
With this priority triggering system, only a few events out of the many
possible will be digitized by the first level trigger, for example, 1
event in 100 possible events. Still fewer, those which after digitization
were noted to be of interest will be stored to the FEBs, for example, 1
event in 100 of those digitized. Of the events which are stored in the
FEBs, the data therein has also been effectively compacted by zero
suppression.
A third level of triggering is provided by the local processor 104. The
local processor by means of various computations, or other system
functions, can preprocess the data stored in the module event buffer to
determine if it contains information which may require further processing.
In this case the module will signal the communications host it has data
ready. If the information the data contains has been totally zero
suppressed or otherwise discounted, the module will not signal the host.
Further, during the transfer of the data from the FEBs to the module event
buffer, the data can be further compress | | |
