An erasable programmable memory device has a number of contiguous data storage cells forming the data memory of the device. The address of one of these data storage cells is stored to designate it as a cell which is to be write protected so that its contents may not thereafter be erased or overwritten. Information is also stored to identify the total number of contiguous data storage cells to be similarly write protected commencing with the cell whose address is stored to designate write protection. The contents of the designated and identified cells are then made permanent. Write protection of the designated and identified cells is accomplished by comparing each write operation address with the addresses of the data storage cells encompassed within the protected area, and if it is within that area, aborting the write operation.

A synchronous memory device of a wave pipeline structure includes: an internal clock signal generation means which generates an internal clock signal being a standard of an output data only during a period in which an output enable signal is activated; and a data transmission means which is connected between an output terminal of a plurality of registers and an output driver, is switched by a control of the internal clock signal, receives data stored in an activated register as input, and transmits the data to the output driver. As a result, the synchronous memory device greatly improves the data access path and the data output hold time, enhances the stability and performance of a memory operation, and achieves a high-speed operation.

According to one embodiment, an apparatus for detecting and preventing tampering with a programmable digital device. The apparatus comprises a one-time programmable (OTP) memory that includes a plurality of memory cells to store data. The plurality of memory cells may be programmed to a default state or a state opposite the default state. A tamper detection circuit is coupled to these memory cells in order to sense a condition when each bit associated with the plurality of memory cells is programmed to the state opposite the default state. In response to detecting this condition, it is considered that the programmable digital device implemented with the apparatus has been tampered with and operations are performed to combat the tampering of the digital device.

A method and apparatus is disclosed for improving the performance of a digital computer by reducing the latency of read operations and increasing available write bandwidth by utilizing a subset of the address bits which are the same from one operation to the next. A faster cycle type (e.g. page mode or static column) can thereby be employed in the Dynamic Random Access Memory (DRAM) memory by eliminating the DRAM precharge and RAS address portions of the cycle.

A process of efficiently managing working storage that unifies the use of queues of fixed size free storage blocks and a global list of blocks of random size. The process implements continuous garbage collection that continually purges unused storage blocks from the fixed size queues to ensure maximum free storage availability. Data processing system throughput is enhanced by reducing the processor overhead required to allocate and return free storage blocks and by reducing the overhead required to manage temporary extensions of working storage.