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Claims  |
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What is claimed is:
1. A communications network adapter comprising:
(a) central random access buffer memory means for storing data at
addressable locations, said buffer memory means being partitioned into
first and second independently and concurrently operating interleaved
banks;
(b) first and second common bus means selectively connectable on an
alternating basis to said first and second banks for providing, on a time
multiplexed basis, address representing signals and data representing
signals to said buffer memory means for storing said data representing
signals therein;
(c) first and second read data bus means selectively connectable on an
alternating basis to said two banks for carrying data representing signals
read out from the memory locations in said buffer memory means specified
by said address representing signals carried by said first and second
common bus means, each of said first and second common bus means and read
data bus means having a finite bandwidth measurable in bits per second;
(d) a plurality of processing means comprising nodes individually coupled
to said first and second common buses and to said read data buses, certain
ones of said plurality of processing means having input/output means for
communication with digital devices connected thereto; and
(e) node control means coupled to said first and second common bus means
and to said first and second read data bus means, said node control means
including memory access control means for synchronously and cyclically
connecting alternate ones of said first and second banks to said first and
second common bus means and said first and second read data bus means,
said node control means further including broadcast means for broadcasting
a processor slot I.D. number to each of said plurality of processing
means, said broadcast means having programmable read-only memory slot
means for storing a plurality of processor I.D. words defining system
profiles, addressing means including counter means and preset switching
means coupled to said programmable read-only memory for reading out said
words defining system profiles as said counter means is advanced, clock
signal generating means for applying regularly occurring timing signals to
said counter means to sequentially advance said counter means to read out
processor slot I.D. words from said programmable read-only memory in a
desired sequence, and a processor slot I.D. bus coupling said processor
I.D. words from said programmable read-only memory means to said plurality
of processing means, and means for selectively assigning access time slots
to said plurality of processing means so that the total aggregate
bandwidth of said first and second common bus means and read data bus
means is allocated to said plurality of processing means on a
predetermined, non-conflicting, need basis.
2. The communications network adapter as in claim 1 and further including
first and second storage protection logic means in said node control means
individually connected to each of said first and second banks, said first
and second storage protection logic means comparing said address
representing signals originating from one of said plurality of processing
means and present on said first and second common bus means to a
predetermined key I.D. assigned to said one of said plurality of
processing means for generating a fault interrupt signal when access to an
unauthorized range of central memory addresses for said one of said
plurality of processors is attempted.
3. A communications network adapter comprising:
(a) central random access buffer memory means for storing data at
addressable locations, said buffer memory means being partitioned into
first and second independently and concurrently operating interleaved
banks;
(b) first and second common bus means selectively connectable on an
alternating basis to said first and second banks for providing, on a time
multiplexed basis, address representing signals and data representing
signals to said buffer memory means for storing and data representing
signals therein;
(c) first and second read data bus means selectively connectable on an
alternating basis to said two banks for carrying data representing signals
read out from the memory locations in said buffer memory means specified
by said address representing signals carried by said first and second
common bus means, each of said first and second common bus means and read
data bus means having a finite bandwidth measurable in bits per second;
(d) a plurality of processing means comprising nodes individually coupled
to said first and second common buses and to said read data buses, certain
ones of said plurality of processing means having input/output means for
communication with digital devices connected thereto;
(e) node control means coupled to said first and second common bus means
and to said first and second read data bus means, said node control means
including memory access control means for synchronously and cyclically
connecting alternate ones of said first and second banks to said first and
second common bus means and said first and second read data bus means,
said node control means further including broadcast means for broadcasting
a processor slot I.D. number to each of said plurality of processing
means, said broadcast means having programmable read-only memory slot
means for storing a plurality of processor I.D. words defining system
profiles, addressing means including counter means and preset switching
means coupled to said programmable read-only memory for reading out said
words defining system profiles as said counter means is advanced, clock
signal generating means for applying regularly occurring timing signals to
said counter means to sequentially advance said counter means to read out
processor slot I.D. words from said programmable read-only memory in a
desired sequence, and a processor slot I.D. bus coupling said processor
I.D. words from said programmable read-only memory means to said plurality
of processing means; and means for selectively assigning access time slots
to said plurality of processing means so that the total aggregate
bandwidth of said first and second common bus means and read data bus
means is allocated to said plurality of processing means on a
predetermined, non-conflicting, need basis; and
(f) interrupt control means in said node control means for generating a
timed sequence of interrupt identifier codes with interrupt bus means
coupling said interrupt control means to said plurality of processing
means for transmitting said interrupt identifier codes to each of said
plurality of processing means, means in each of said processing means for
decoding a different one of said interrupt identifier codes assigned to it
for allowing any of the plurality of processing means responding to its
interrupt identifier code to place on said interrupt bus means an
interrupt request and a processor identifier code for identifying a
destination processor to which said interrupt request is directed, and
interrupt processor means coupled to said interrupt bus means for
receiving said interrupt requests and said processor identifier codes of
the destination processors for routing interrupt data to identified ones
of said plurality of destination processors in accordance with a
predetermined priority assignment.
4. The communications network adapter as in claim 3 wherein said interrupt
processor means includes a dedicated storage means for storing at
addressable locations route maps containing priority levels, destination
and origin information of the interrupting and interrupted ones of said
plurality of processing means. |
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Claims |
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Description |
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BACKGROUND OF THE INVENTION
I. Field of the Invention
This invention relates to an improved type of network communications
adapter of the type used to provide high speed digital communications
between a multiplicity of computing resources both co-located and
geographically dispersed.
II. Discussion of the Prior Art
Prior art network communications adapters generally comprise one or more
nodes where such node is the digital interface circuitry required to
connect a computing resource, such as a computer a printer, or a mass
storage device to the network. The computers may range from a super
computer, such as the Cray II, a 64-bit main frame computer to any one of
a variety of present-day 16-bit minicomputers. A single node may also
accommodate a multiplicity of slower devices, e.g., 8-bit personal
computers and terminals. The device/node interface is typically a
high-speed parallel interface exemplified by the IBM block multiplexer
channel type of input/output.
Within a local geographical area, the communication media preferably
comprises one or more multi-drop coaxial serial data links or,
alternatively, fiber-optic serial data links. This local connection will
hereafter be referred to as the "trunk". A complete communication network
may be comprised of a multiplicity of trunks which are linked together by
commercial common-carrier communication services, e.g., telephone company
T1-type trunk line. The network communication adapter functions to provide
a virtual connection between a device coupled to the node and another
device on another node to which the first device can present a request to
communicate. The functions of a network communications adapter, well
understood in the prior art, are as follows.
Data from the adapter's host is received, on demand, in a continuous or
intermittent stream of data. This data stream is divided into a sequence
of data blocks. To each block of data is added a message header
identifying the source and the destination of the data block and following
the data block is a message trailer providing error correction
information. The data block with its associated header and trailer is
called a message packet. By means of controlled contention with other
network adapters, the transmitting adapter gains access to the trunk and
link network resources required to transmit the message packet to the
destination adapter. Message packets from a multiplicity of sources are
sent in a time division multiplex manner over a single serial trunk or
link network medium. Each network adapter screens all messages present on
its trunk(s) and captures only those messages whose address matches the
identification number of the adapter node. Each received packet is checked
for correctness, the receipt thereof is acknowledged to the sender, the
header and trailer are stripped off and the data formatted and presented
to the receiving host computer or other digital device coupled to the
receiving adapter.
Various techniques to assure data integrity even in the presence of noise
and other perturbations on the network are well known in the prior art. In
an ideal communication network, all devices would be able to communicate
freely with any other devices in the network at their maximum data rate.
In a real network, however, the data rate limitations of the trunk
establish an upper limit on the number and rate of messages which can be
accommodated. Any communication between devices through the network
consumes a portion of this aggregate bandwidth regardless of the
geographical distance spanned.
It is one object of this invention to provide a multi-node network adapter
with a unique architecture which provides for very high data rate
communication between the nodes of a given adapter without using the
communication trunk, thereby conserving data bandwidth. With this
invention, the aggregate data bandwidth of the network adapter can
substantially exceed the aggregate bandwidth of the communication trunks
employed.
In prior art communication systems, it is typically required that one of
the host computers be designated as the network controller to manage or
oversee message traffic across the entire network. The program which
accomplishes this, the Network Executive, is generally run on a large main
frame computer in a multi-tasking environment. For a large high
performance network, the network executive can consume a significant
fraction of the available computing capability of a relatively expensive
main frame computer.
It is thus a further object of this invention to provide a novel
communications adapter architecture in which a relatively inexpensive
microprocessor can perform the network executive function.
It is a yet further object of this invention to provide a common,
high-speed buffer memory which is shared by all of the node processors
within a given network communications adapter.
A still further object of this invention is to provide a novel interrupt
system which enables efficient coordination between the various node
processors to facilitate the high speed flow of data messages.
Large telecommunication systems typically require a diverse range of
communication interface hardware. One example might be a communications
concentrator where a large number of slower speed devices are combined to
appear as a single node on a communications trunk. In this case the
channel bandwidth of the communications concentrator must be spread among
a large number of interfaces. Another example is a "gateway adapter" which
provides a communications bridge between two high-speed communication
trunks. In this instance, all of the channel bandwidth is dedicated to a
single communications path. In prior art systems, each type of
communication device is typically a different product, each specialized to
perform its particular function in the total system.
It is thus a yet further object of this invention to provide a network
adapter which can be configured out of a common set of modular elements to
perform a large number of different communications functions in that once
configured, the aggregate channel bandwidth of the adapter can be
selectively divided among various users to provide optimal throughput
performance.
SUMMARY OF THE INVENTION
The foregoing objects and advantages are achieved by providing a
communication network adapter having a random access buffer memory, which
is partitioned into first and second independently and concurrently
operating interleaved banks, and to which a plurality of processors may
individually be coupled via first and second common buses which are
selectively connectable, on an alternating basis, to the first and second
banks to allow addresses and data to be transferred therebetween. In
addition to the random access buffer memory, the network adapter also
includes node control circuitry for synchronously and cyclicly connecting
the first and second interleaved banks to the communication buses whereby
a process slot I.D. number can be broadcast to all of the processors
coupled thereto. As such, the available bandwidth of the communication
buses is effectively allocated to the plural processors, but only the one
of the processors having a matching I.D. number is capable of exchanging
data with the buffer memory during a given time interval.
The communication network adapter of the present invention also includes an
improved interrupt control arrangement in which interrupt identifier codes
are generated in a timed sequence and transmitted over a separate
interrupt bus to the plural processors. The processors, then, include
circuitry for responding to an interrupt identifier code assigned to that
given processor, allowing that processor to present an interrupt request
and a processor identifier code identifying a particular processor which
is to receive that request. Once an interrupt processor connected to the
interrupt bus receives the interrupt request and an I.D. code for the
destination processor, interrupt data is transmitted to the designated
destination processor in accordance with an established priority
assignment.
These and other objects and advantages of the invention will become
apparent to those skilled in the art from the following detailed
description of a preferred embodiment, especially when considered in
conjunction with the accompanying drawings in which like numerals in the
several views refer to corresponding parts.
DESCRIPTION OF THE DRAWINGS
FIG. 1 is a system block diagram of the network communications adapter of
the present invention;
FIG. 2a and FIG. 2b are waveforms illustrating the timing signals required
for operation in the system of FIG. 1;
FIG. 3 is a more detailed block diagram of the node control circuitry in
the block diagram of FIG. 1;
FIGS. 4a and 4b, when arranged as in FIG. 4 is a more detailed block
diagram of the central memory portion of the block diagram of FIG. 1;
FIG. 5 is a detailed block diagram of the 32-bit nucleus microprocessor;
FIGS. 6a through 6d, when arranged as in FIG. 6; is a detailed block
diagram of the 16-bit microcontroller used in the communications network
adapter of FIG. 1;
FIGS. 7a and 7b, when arranged as in FIG. 7 is a block diagram
representation of the DMA circuitry;
FIG. 8 is a detailed block diagram of the DMA controller used in the direct
memory access circuitry of FIG. 7;
FIG. 9; is a detailed block diagram of the Bank 0 storage protection
circuitry of the node control of FIG. 3;
FIG. 10 shows a detailed block diagram of the access control circuitry
portion of the node control of FIG. 3;
FIGS. 11a and 11b when arranged as in FIG. 11,; is a detailed block diagram
representation of the interrupt control of FIG. 3;
FIGS. 12a-1 and 12a-2 when arranged as shown in FIG. 12 show a detailed
block diagram of the Interrupt Processor of FIG. 5; and
FIG. 13 depicts the organization of the data linkage structure utilized.
DESCRIPTION OF THE PREFERRED EMBODIMENT
NETWORK ADAPTER SYSTEM
FIG. 1 shows a system level block diagram of the network adapter of the
present invention. The hub of the adapter is Central Memory 100, which
preferably may be a high speed static random access memory (SRAM)
organized into two interleaved banks identified as Bank 0 and Bank 1.
Communication between Central Memory 100 and all processors within the
adapter is via buses 102, 104, 106 and 108. The common bus 102 will be
referred to as the A bus and the common bus 104 will be referred to as the
B bus. Each contains 24 lines which are time multiplexed to provide either
a 24-bit address or 16-bits of write data to the central memory 100. The A
"read" bus 106 and B "read" bus 108 each provide 16 bits of read data from
the central memory 100. The state of the Bank/Bus select line 138
determines the connection of the A or B buses to the Central Memory 100.
For example, when line 138 is low, the A buses 102 and 106 are connected
to Bank 0 while the B buses 104 and 108 are connected to Bank 1. When line
138 is high, this connection is reversed.
The dual 16-bit architecture provides efficient coupling between the
Central Memory 100 and a mix of 32-bit microprocessors, such as identified
as numerals 110 and 112, and 16k -bit microcontrollers as at 114, 116 and
118. Microprocessors 110 and 112, along with microcontrollers 114 through
118, provide a typical example of how the network adapter of the present
invention can be configured. This arrangement is to be considered
illustrative only, and not limitive. Actually, the architecture
accommodates any mix of processors, typically up to a total of 16. Each
network has a 32-bit microprocessor, such as 110, dedicated to the
internal control of the network adapter. This dedicated processor,
hereafter referred to as the "Nucleus Processor", manages the routing of
message traffic through the adapter, and particularly, manages the
dynamic, page-by-page assignment of central memory space. Additional
32-bit microprocessors, such as that identified by 112, may be optionally
added to perform specific application programs within the adapter, e.g.,
the aforementioned network executive function.
The 32-bit microprocessor functioning as the Control Processor has a dual
RS 232-C serial I/O port 120 and 122 to which various peripheral digital
devices may be connected in a conventional manner. Processors 114 through
118 may preferably be 16-bit high-speed bit slice microcontrollers in
which the architecture and the firmware has been carefully tailored to
provide efficient high speed I/O handling functions. In explaining one
system configuration, processor 114 is assumed to be a Node Processor
which is dedicated to a single, large-scale, high-speed digital computing
device, here designated as "Host 1" Communication is via a 16-bit,
bi-directional, high-speed parallel channel on bus 124. Processor 116
performs the same function for a second device designated as "Host 2", via
parallel bus 126. Alternatively, a single processor might be configured to
interface to a multiplicity of lower speed devices, such as printers or
video displays. The 16-bit processor 118 provides a way of connecting the
network adapter of the present invention to a network by way of a serial
trunk line 128.
Processors 110 and 112 are shown as communicating with Central Memory 100
in a 32-bit mode by virtue of being concurrently connected to both the A
and B buses. Each 32-bit transfer generally involves 16 bits from Bank 0
and 16 bits from Bank 1. Processors 114 and 118 are configured to
communicate with Central Memory 100 in a 16k -bit mode via the A common
bus while processor 116 is shown as communicating with Central Memory 100,
via the B common bus.
An important feature of this network adapter architecture is that
processors 114 and 116 may be simultaneously serviced during a given
central memory cycle. Further, the dual bank architecture employed enables
a 16-bit processor to write a contiguous block of data in Central Memory
100 which can be read contiguously by a 32-bit processor in spite of the
disparity of word length. Similarly, data contiguously written in a 32-bit
mode by either processors 110 or 112 can be contiguously read in a 16-bit
mode by processors 114 through 118.
To maintain the highest possible data rate in and out of Central Memory
100, all data transfers are synchronous and under the control of Node
Control logic 130. At the beginning of each memory cycle, Node Control 130
broadcasts the processor slot I.D. number of the processor designated to
have access to either the A or B bus via bus 132. It contains two 4-bit
processor slot I.D. codes, one associated with the A bus and the other
associated with the B bus. The processor I.D. bus 132 also contains the
state of Bank/Bus select line 138. At this point, it is necessary to
understand that each of the processors has an established processor I.D.
code which is determined by the setting of manual DIP switches within the
processor and which are set at the time of system installation. When the
processor slot I.D. codes broadcasted on bus 132 match a given processor
I.D. code and address bit 01 corresponds to the state of the Bank/Bus
select line 138, that processor may execute a memory transfer operation.
Each memory cycle has two phases. During the first phase, the enabled
processor puts the memory address on the common bus. More particularly,
thirty-two bit processors put identical addresses on both the A and B
common buses 102 and 104 while 16-bit processors access only their
dedicated common bus. During the second phase of the memory cycle, data
from the addressed memory cell is read on either the A read bus, B read
bus or concurrently on both A and B buses. Alternatively, in the event of
a write cycle, the write data is placed on the respective common bus.
With this arrangement, both processors 114 and 116, or, alternatively,
processors 116 and 118 might operate concurrently during a given memory
cycle over their respective A and B buses. To accomplish this, Node
Control 130 places the processor slot I.D. code associated with processor
114 on the A section of the slot processor I.D. bus and places the
processor I.D. code associated with the processor 116 on the B portion of
the slot processor bus.
Storage protection of Central Memory 100 is enforced by Node Control 130,
such that each processor may only write into the pages of memory to which
it has been given key access privilege. Node Control 130 maintains a table
of processor access privilege, by page, in a RAM memory. This memory is
initialized upon application of power and may be subsequently modified by
the Nucleus Processor 110. Each processor and each DMA has a set of DIP
switches which provide its key identity. Generally, each processor and DMA
has its own processor I.D. but will share a common key I.D. when
associated with one another. When enabled, 32-bit processors put their key
I.D. code on both the A and B sections of key bus 134 while 16-bit
processors place their key I.D. code on only that section of the key bus
corresponding to the particular memory bus to which they are attached. If
any processor attempts to write into a page of central memory 100 which is
not assigned the identical A and/or B keys, this condition is detected by
Node Control 130, which then generates a "memory fault" interrupt to
Nucleus Processor 110, via the interrupt bus 136.
Interrupt bus 136 is a polled, bi-directional bus under the control of Node
Control 130. When polled, each processor may direct a multi-level
interrupt to any other processor in the adapter. End-to-end response time
for any interrupt is guaranteed to be less than 5.2 microseconds providing
an efficient, high-speed mechanism for coordinating the interoperation of
the other network adapter processors.
MESSAGE FLOW
To help provide a context for the detailed description of the network
adapter which will follow, it is instructive next to consider the overall
operation of the system and, in particular, the manner in which data or
messages flow through the system.
A message is passed from Host 1 to another device on serial trunk 128 in
the following manner. Nucleus Processor 110 assigns buffer space for the
message in the Central Memory 100. Microcontroller 114 contains direct
memory access logic to transfer the incoming message from Host 1 to
Central Memory 100 in the assigned space. Concurrently microcontroller 118
transfers data from the buffer space of Central Memory 100 to the serial
trunk 128 using identical DMA hardware. Upon receipt of the command from
Host 1 to transmit a message, microcontroller 114 interrupts Nucleus
Processor 110 which assigns buffer space in Central Memory 100 and sets
the storage protect table in Node Control 130 to enable write access by
microcontroller 114. Nucleus Processor determines, by means of a routing
table, which microcontroller will be the destination or route of the
message. The designated microcontroller is interrupted and provided with a
pointer to the buffer area of Central Memory 100 where the outbound
message is assembled. The software and hardware control structure is
arranged to enable a large number of concurrent messages to be processed.
As already indicated, a network adapter in accordance with the present
invention, may be comprised of typically up to 16 processors where each
processor may handle a multiplicity of concurrent or interleaved messages.
Limitation to this number, however, should not be inferred. A detailed
description of how message flow is controlled is provided in a following
section titled "Software Control Structure".
SYSTEM TIMING
FIGS. 2A and 2B show typical timing signals required for operation of the
network adapter. The source of all adapter timing is a single 50 MHz
crystal controlled oscillator in node Control 130. This signal is
broadcast to Central Memory 100 and all processors as the 50 MHz clock
150. Node Control 130 also broadcasts a second signal, the time 0 signal,
152. Care must be taken in the fanout and distribution of these signals to
maintain an acceptable range of delay times, T1 and T2, and to further
minimize the skew between clock signals arriving at different points in
the system. An acceptable variation in the delay time for times T1 and T2
is from 4 nanoseconds minimum to 16 nanoseconds maximum. From the signals
150 and 152, each section derives four other clock signals, identified in
FIG. 2A as 154-160, which will be referred to hereafter as the "T 20"
clock, "T 40" clock, "T 80" clock and the "T 160" clock, respectively.
Care must also be exercised in the fanout and distribution of these last
mentioned clock signals to minimize skew relative to the 50 MHz clock so
as to assure reliable synchronous operation.
The T 20 clock and T 40 clock are used to derive the central memory timing
signals shown in FIG. 2B. The "Access Request" signal 184 controls the
initiation of a memory cycle. Signal 186 shows the typical waveforms of
the higher order bits 16 through 23 of the common bus. The unshaded region
192 shows the period of the memory cycle in which the address information
is valid. Similarly, signal 188 shows typical waveforms on the lower order
bits 0-15 on the same bus. It should be recalled that 16 bits of data are
time multiplexed with the lower 16 bits of the address. Thus, unshaded
region 194 shows the time during which the address info | | |
