A multi-board computer system is described which comprises a main circuit board, a first circuit board having a third surface and a fourth surface opposite the third surface, and a second circuit board having a fifth surface. The main circuit board further includes means for generating a first board select signal to select the first circuit board and a second board select signal to select the second board. The first circuit board further includes a first input pin and a second input pin on the third surface, and a first output pin on the fourth surface. The first input pin corresponds to the first output pin. The first input pin is coupled to receive the first board select signal, and the second input pin is coupled to receive the second board select signal. The first circuit board is selected when it receives the first board select signal at the first input pin. The second circuit board further includes a third input pin. The third input pin is coupled to the first output pin of the first circuit board. The second circuit board is selected when it receives the second board select signal at the third input pin. The first circuit board further includes position shifting means for coupling the second board select signal from the second input pin of the first circuit board to the first output pin of the first circuit board. When the second input pin of the first circuit board receives the second board select signal, the position shifting means couples the second board select signal to the third input pin of the second circuit board via the first output pin. A method of selecting a circuit board in the multi-board computer system is also described.

A graphic processor which controls reading, writing and transfer of graphic data for a display memory that stores graphic data. The processor includes a first unit which stores first address information for addressing the display memory and first pixel address information which points a pixel position in a word specified by the first address information, a second unit which stores second address information for addressing the display memory and second pixel address information which points a pixel position in a word specified by the second address information, a third unit which shifts graphic data of multiple pixels included in two consecutive words to extract continuous 1-word graphic data, and a fourth unit which implements drawing computations pixel-wise concurrently for one word depending on the number of pixels included in a word. Even if transfer source graphic data lies across two consecutive words, the processor fetches the source data in single reading, processes the data word-wise at once, and stores the result in the display memory.

An apparatus for transferring data between a computer system having a first architecture and a slave element having a second architecture. The apparatus includes a first connector corresponding to the first architecture, a second connector corresponding to the second architecture, and conversion circuitry located between the first connector and the second connector. The conversion circuitry converts signals corresponding to the first architecture to signals corresponding to the second architecture and signals corresponding to the second architecture to signals corresponding to the first architecture.

Security from an unwanted intrusion into a computer system is provided by coupling a host component with a peripheral component using a high-speed serial bus having a high-speed physical layer and using features of the bus to implement the security. In an embodiment, the high-speed serial bus has a secondary bus layer that is used to implement a number of the security features of the invention.

Method and apparatus for enabling configuration of a PCI daughter card residing on an MCA adapter card using MCA setup cycles and signals and for ensuring the allocation of memory space to the daughter card. In a preferred embodiment, the invention comprises an MCA adapter card connected to an MCA system bus of a conventional PC. A PCI-compliant daughter card, the purpose of which is to provide additional functionality to circuitry of the adapter card, resides on a PCI bus of the adapter card. A PCI/MCA bridge is provided for interfacing the MCA system bus with the PCI bus of the adapter card for enabling configuration of the daughter card during the setup sequence of the MCA bus and to respond with an appropriate ROM signature during DOS boot-up to ensure that memory space will be allocated to the daughter card, if needed. A first set of XPOS registers of the adapter card are used selectively to enable the bridge and to allow the PCI configuration space, or registers, of the daughter card and other PCI-compliant devices on the daughter card to be selectively accessed and initialized. Certain registers of a second set of XPOS registers are used to set the data flow mode of the bridge and to respond with the correct ROM signature at DOS boot-up of the PC. The remaining ones of the second set of XPOS registers are used selectively to enable and to store the size and location of any necessary RAM and/or ROM apertures of the daughter card, thereby enabling the bridge to initiate a PCI operation to the daughter card if it decodes an address within either of the apertures.