 |
Description  |
|
|
BACKGROUND OF THE INVENTION
The invention of the parent patent relates generally to adaptive
"single-bit" (delta and delta-sigma modulation) digital encoding and
decoding systems for high-quality audio signals in which the message
frequency band extends from very low audio frequencies, in the order of 20
to 50 Hz, to about 15 kHz. However, the invention is not limited to such
applications. In particular, the invention of said parent patent relates
to such systems in which the adaptive function, by means of an adaptive
filter, variably divides the message frequency band into delta and
delta-sigma modulation regimes of operation. The invention of this
division relates to a circuit for providing an adaptation control signal
responsive to the amount of information carried by the bit stream
("bit-stream loading").
A simple single-integration delta modulator is a type of single-bit digital
encoder that encodes an audio signal as a series of ones and zeros in such
a way that the average number of ones over a short period of time
represents the instantaneous slope of the audio signal. Each one-bit word
of the bit stream tells the delta modulation decoder to take one step up
or down to reconstruct the audio. The size of this step is a parameter of
the design: small steps give small quantization errors but limit the
maximum slope of the signal, and steps large enough to accommodate
high-frequency high-level signals produce large quantization errors. An
adaptive delta modulator changes the step size dynamically, attempting to
provide an acceptable compromise between quantization-error level and
high-frequency signal handling ability.
In a delta-sigma modulator, which is also a single-bit digital device, the
average number of ones over a short period of time represents the audio
signal itself instead of its slope. Thus, the delta-sigma modulator,
unlike the delta modulator, has an overload characteristic that is
independent of frequency. Adaptive delta-sigma modulation systems are also
well known.
A common way to implement delta modulation encoders and decoders is to
obtain the integration function by using a fixed-frequency low-pass filter
having a corner (pole) frequency low in the message signal band (300 Hz in
a prior art high-quality audio delta-modulation system). Such an
arrangement is sometimes referred to as a "leaky integrator": below the
corner (turnover) frequency of the filter (the "leak" frequency or "leak
time constant"), the modulator acts as a delta-sigma modulator and, above
the corner frequency, the modulator acts as a delta modulator. In adaptive
systems, the gain of the fixed-frequency low-pass filter integrator is
varied to achieve the adaptation. It appears that circuit designers have
used leaky integrators for two principal reasons: a leaky integrator,
unlike a pure integrator, does not require infinite gain at low
frequencies; and a leaky integrator, unlike a pure integrator, quickly
dissipates errors in the bit stream due to its relatively short time
constant. The invention of the parent patent recognizes that the division
of the message signal band into delta modulation and delta-sigma
modulation regimes of operation is desirable, but that further improvement
in performance and simplicity of operation can be achieved by dynamically
varying the frequency at which the message band is divided into the two
regimes of operation. This is accomplished by dynamically varying the
corner (pole) frequency of the leaky integrator as the adaptive parameter
of the system and by allowing, under certain signal conditions, the corner
frequency of the leaky integrator to assume frequencies relatively high in
the message signal band.
In any adaptive single-bit digital encoding and decoding system, circuitry
is required to determine the amount of adaptation needed at any given
time. Many prior art adaptive delta modulators operate in the digital
domain to determine the required adaptation, using various bit-counting
algorithms and circuits to increase the step size when long strings of
ones or zeros are encountered in the encoded digital audio bit stream.
Other prior art delta-modulator adaptation-control circuits operate in the
analog domain, typically employing techniques similar to those used in the
control circuits of analog audio compressors and expanders, including the
use of "speed-up" networks to minimize overload at the onset of
transients. The control circuit of the present invention, although
operating also in the analog domain, recognizes that the encoded digital
bit stream carries audio information particularly well suited for adaptive
control and that the audio information can be simply derived and processed
as an analog signal for use as an adaptation control signal.
SUMMARY OF THE INVENTION
In accordance with one aspect of the invention of the parent patent, the
adaptive function in a single-bit digital encoding and decoding system is
provided by dynamically dividing the message frequency band into first and
second regimes of operation in response to an adaptation control signal,
the adaptation function in the portion of the message frequency band
subject to the first regime of operation acting in the manner of
delta-sigma modulation, and the adaptation function in the portion of the
message frequency band subject to the second regime of operation acting in
the manner of delta modulation. In a preferred embodiment, this is
implemented by varying the low-pass filter corner frequency of a leaky
integrator as opposed to prior art arrangements having a fixed-frequency
low-pass filter and a variable-gain leaky integrator. Thus, the
arrangement operates as a delta-sigma modulator below the filter corner
frequency and a delta modulator above that frequency. The corner frequency
of the variable low-pass filter, under certain signal conditions, assumes
frequencies relatively high in the message frequency band in comparison to
the low fixed corner frequencies (near the bottom of the message band)
typically used in prior art leaky integrators.
According to this aspect of the invention of the parent patent, a
variable-frequency single-pole low-pass filter performs the adaptive
function by adjusting the transition frequency between the delta and
delta-sigma regimes in response to a control signal. There is no
requirement to vary the gain of the integrator. Thus, the variable
low-pass filter, or variable "leaky integrator," simply and inexpensively
provides the delta-modulation integration function at frequencies above
its variable cutoff frequency, thereby providing an integrator whose
integration frequency changes but whose gain at frequencies below the
filter cutoff frequency does not change. As the cutoff frequency shifts,
the integration gain above the cutoff frequency changes due to the
shifting of the single-pole low-pass filter characteristic, which rolls
off at 6 dB/octave, in the preferred embodiment.
This novel arrangement is believed to provide improved signal-to-noise
performance, particularly with respect to low-frequency noise in the
presence of high-level high-frequency signals, by taking advantage of the
characteristics of delta and delta-sigma modulators and demodulators in
response to dynamically changing signal conditions. The arrangement also
retains the advantage of the decreased sensitivity of leaky integrators to
integration errors. In addition, in practical circuit implementations,
since variable-frequency low-pass filters have constant gain at low
frequencies and DC, offsets at the input of the adaptive filter circuit
are not likely to cause audible thumps when the filter frequency changes
rapidly.
In a preferred embodiment, the variable frequency low-pass filter is
realized by placing broad-band negative feedback around an integrator
whose gain can be varied. At frequencies where the forward gain through
the integrator exceeds the feedback factor by a sufficient margin, the
frequency response is the inverse of that of the feedback network--a flat
response. At higher frequencies, the forward gain of the integrator is
smaller than the feedback factor, and the overall response becomes that of
the integrator. In this way the frequency at which the response changes
from flat to integration changes as a function of the gain of the
integrator: the circuit functions as a variable-frequency single-pole
low-pass filter.
In a preferred embodiment, the circuit includes an additional shelving
low-pass filter in cascade with the variable filter. This additional
filter serves both as a fixed pre- (in the encoder) and de-emphasis (in
the decoder) network, reducing the audibility of noise modulation, and as
a second integrator, providing noise shaping and improving the idle
pattern of the modulator. In addition, in the preferred embodiment of the
encoder, a further shelving low-pass filter is located in the feedback
loop to the input comparator for the purpose of additional noise shaping.
According to the invention of this division, an adaptation control-signal
generator measures the effective "bit-stream loading" to generate a
control signal for adjusting the variable low-pass filter frequency.
Bit-stream loading is an indicator of the amount of information carried by
the encoded audio bit stream. The adaptation control-signal generator
according to this invention operates in the analog domain to provide a
simple, yet effective, means to maintain a high bit-stream loading. In
addition, the adaptation control-signal generator of this aspect of the
invention is inherently capable of quick response due to the nature of its
rectifier and smoothing circuits, and does not need extra "speed-up"
networks used in certain prior art adaptation circuits to minimize
overload at the onset of transients. This aspect of the invention is also
usable with conventional delta-modulation systems, including the
aforementioned variable-gain, fixed-frequency leaky integrator
arrangement.
Because a delta-modulation signal can be decoded using an integrator, the
audio content of a delta-modulation bit stream can be thought of as the
time-derivative of the decoded audio signal produced when that bit stream
is integrated. The derivative of an audio signal is, of course, its slope.
This aspect of the invention is based on the recognition that because an
adaptive delta modulator adjusts step size in response to changes in slope
(an ideal adaptive delta modulator, for example, always accommodates the
slope of an applied audio signal), the audio content of the bit stream, an
indicator of slope, is well suited for use in adjusting the slope handling
ability of a delta modulation system or a hybrid delta/delta-sigma
modulation system. As the audio content of the bit stream (the bit-stream
loading) rises, it indicates the presence of more and more information in
the bit stream and that the delta modulator is approaching slope
overloading. Ideally, the information in the bit stream is maximized
without slope overloading.
In accordance with the teachings of the invention of this division, the
audio content of the bit stream is transformed to the analog domain,
rectified and smoothed. Optionally, the rectified and smoothed signal is
then applied to a non-linear circuit such as an exponentiator, square-law,
or cube-law device, which provides the control signal to the adapting
element in a feedback-loop arrangement. In some applications, the
non-linear circuit may be omitted. Either with or without the non-linear
circuit, an analog audio compressor-type action is achieved. With the
non-linear circuit, as the bit-stream loading increases to higher and
higher levels, the degree of adaptation increases at an ever increasing
rate and approaches a finite limit analogous to pure limiting in a
compressor. In the case in which the non-linear circuit is omitted, a
constant compression ratio results, determined by the gain in the control
circuit.
In a preferred embodiment of the invention, the audio content of the bit
stream can be transformed to the analog domain by applying the encoded bit
stream to a fixed low-pass filter having a corner frequency just above the
message frequency band, but below the clock frequency used to produce the
bit stream, so that the clock signal component, at a frequency above the
audio band, is removed. The filter output, an analog signal, is peak
rectified, smoothed by a non-linear time constant and applied to the
optional non-linear circuit for application to the control input of the
variable low-pass filter. The filter cutoff frequency is a linear function
of the applied control signal. As the peak bit-stream loading increases,
the cutoff frequency of the variable low-pass filter increases.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a functional block diagram of a preferred embodiment of the
invention of the parent patent embodied in a modulator or encoder,
incorporating both the first aspect of the invention, the
variable-frequency low-pass adaptive filter, and the second aspect of the
invention, the adaptation control-signal generator responsive to
bit-stream loading.
FIG. 2 is a functional block diagram of a preferred embodiment of the
invention of the parent patent embodied in a demodulator or decoder.
FIG. 3 shows a set of theoretical response curves (gain versus frequency
(logarithmic scale)) for the variable-frequency filters 14 and 14' of
FIGS. 1 and 2, respectively, showing, in solid lines, the quiescent
low-frequency extreme position of the filters and the high-frequency
extreme position of the filters, which is approached as a limit, and, in
dashed lines, several example of intermediate positions.
FIG. 4 shows the theoretical response curve for the single-pole low-pass
shelving filters 16 and 16' of FIGS. 1 and 2, respectively.
FIG. 5 shows the theoretical response curve for the single-pole low-pass
shelving filter 17 of FIG. 1.
FIG. 6 shows the theoretical combined response curve for the single-pole
low-pass shelving filters 16 and 17 of FIG. 1.
FIG. 7 is a schematic circuit diagram of a practical implementation of the
preferred encoder embodiment.
FIG. 8 is a schematic circuit diagram of a practical implementation of the
preferred decoder embodiment.
FIG. 9 is a schematic circuit diagram showing a modification to the control
circuit portion of FIGS. 7 and 8.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring now to the drawings, FIG. 1 shows a functional block diagram of a
preferred embodiment of the invention embodied in a modulator or encoder,
incorporating both the invention of said parent U.S. Pat. No. 4,829,299,
the variable-frequency low-pass adaptive filter, and the the invention of
this division the bit stream loading responsive adaptation control-signal
generator. FIG. 2 is a functional block diagram of a preferred embodiment
of the invention embodied in a demodulator or decoder. Because the encoder
includes the decoder, only the encoder of FIG. 1 will be described in
detail. Corresponding functional elements of the decoder that are also
present in the encoder generally are labeled with the same reference
numeral but with a prime mark ("'") in the decoder of FIG. 2.
Referring to FIG. 1, the analog audio input is applied to input terminal 2
which is fed to a subtractor 6 that calculates the difference between the
applied input audio signal and the reconstructed analog audio signal at
the output of the encoder's local decoder. This difference is quantized to
one of two binary levels by an operational-amplifier comparator 8 and is
then time sampled by a D flip-flop 10 which is clocked by the clock input
at terminal 4. The D flip-flop 10 provides the encoded digital signal
output to output terminal 12 and to the variable-frequency low-pass filter
14. Subtractor 6, filter 17 (described below), comparator 8, and flip-flop
10 comprise digitizing means responsive to the two analog signals applied
to subtractor 6 and to the clock sampling signal from terminal 4 applied
to the flip-flop 10 for generating the digitally encoded output signal
available at terminal 12; the output signal is a digital bit stream in
which each single digital bit is responsive to a function (the filtered
difference) of the two analog signals at each clock time.
FIG. 3 shows a set of theoretical response curves for the
variable-frequency filters 14 and 14', showing the low-frequency quiescent
position and the high-frequency limiting position of the filter in solid
lines and several examples of intermediate positions in dashed lines. The
filter corner frequency, of course, may assume substantially an infinite
number of positions in response to the DC control signal.
The output of variable-frequency low-pass filter 14 is fed to a low-pass
shelving filter 16 which provides the local analog decoder signal
(available at terminal 11) for application to the inverting input of
subtractor 6. Filter 16 provides a fixed pre-emphasis in the encoder;
filter 16' provides a fixed de-emphasis in the decoder. Both filters 16
and 16' provide noise shaping and act as a second integrator. FIG. 4 shows
the theoretical response curve for the low-pass single-pole shelving
filters 16 and 16'. The break frequencies f.sub.1 and f.sub.2 of the shelf
response are discussed below in connection with the practical embodiments
of FIGS. 7 and 8. In the encoder of FIG. 1, the filter 16 provides a
pre-emphasis effect because it is contained in the feedback loop applied
to subtractor 6. Thus, in the encoder its response provides a boost rising
at 6 dB/octave between f.sub.1 and f.sub.2, which is complementary to the
response shown in FIG. 4. In the decoder of FIG. 2, the filter 16'
provides a de-emphasis effect in accordance with the response shown,
namely, a roll off falling at 6 dB/octave between f.sub.1 and f.sub.2.
A further low-pass shelving filter 17 is provided in the encoder between
subtractor 6 and comparator 8. Filter 17 provides additional noise shaping
in the encoder, carrying the noise shaping down to a lower frequency than
provided by filter 16. The placement of filter 17 is such that it has no
effect on the preemphasis and has only a very small effect on the overload
capability of the encoder. FIG. 5 shows the theoretical response curve for
the low-pass shelving network 17. The break frequencies f.sub.3 and
f.sub.4 of the filter 17 shelf response are discussed below in connection
with the practical embodiments of FIGS. 7 and 8. Break frequency f.sub.1
of filter 16 and break frequency f.sub.4 of filter 17 are nearly the same.
Thus, in the encoder, the cascade arrangement of filters 16 and 17 results
in a combined response that is also a low-pass shelving characteristic.
FIG. 6 shows the theoretical combined response curve for filters 16 and
17.
The digital bit stream from the D flip-flop 10 is also applied to the
adaptation control signal generator 18 which applies a control signal to
the variable-frequency filter 14 to control its corner (cutoff) frequency.
The adaptation control signal generator 18 includes a low-pass filter 20,
a full-wave peak-responding rectifier 22, a smoothing circuit 24, and
(optionally) a non-linear circuit, a circuit embodying a function having a
monotonically increasing slope, such as an exponentiating circuit 26.
Although a square-law or cube-law circuit is suitable, in practice, an
exponentiating circuit is used because such a circuit is easily
implemented using bipolar transistors. Although improved performance is
obtained when the optional non-linear circuit is used, in some
applications it may be desirable to omit the non-linear circuit. In the
decoder shown in FIG. 2, the digital input 28 accepts a digital signal
such as provided at output 12 of the encoder of FIG. 1. The audio output
signal at terminal 30 of the decoder is a close replica of the audio input
signal at terminal 2 of the encoder of FIG. 1 when the decoder receives an
encoded digital signal from the encoder of FIG. 1. A D flip-flop 10' is
provided in the input of the decoder of FIG. 2 in order to provide a very
clean digital bit stream to the adaptive filter 14'.
FIGS. 7 and 8 are schematic circuit diagrams of practical implementations
of the preferred embodiments of the encoder and decoder, respectively,
which implement the functions described in connection with the embodiments
of FIGS. 1 and 2. In the manner of FIGS. 1 and 2, only the encoder, FIG.
7, will be described in detail because it includes all of the elements of
the decoder. Corresponding elements of the decoder that are also present
in the encoder generally are labeled with the same reference numeral but
with a prime mark in the decoder. Pin numbers of solid-state devices are
designated by the reference number of the device, a hyphen and the pin
number. Thus, for example pin 3 of the device 102 is designated as 102-3.
The description of FIG. 7 begins with circuit elements common to the
encoder and decoder.
Referring to FIG. 7, a single-pole low-pass variable-frequency filter is
effectively in series with a low-pass shelving filter. The
variable-frequency filter is implemented by a variable-gain integrator
within a feedback loop. The variable-gain integrator includes a variable
transconductance amplifier 102, driven at its positive and negative
inputs, 102-16 and 102-15, respectively, by current source resistors 301
and 302 so as to operate as a variable current-gain amplifier. The
variable-gain integrator also includes an operational amplifier 103,
receiving the output of amplifier 102 from pin 102-13 of device 102 at its
input pin 103-2, an capacitor 202. The local decoder output, an analog
audio signal, taken from the output pin 103-1 of device 103 is provided at
output terminal 54. In the decoder, the analog audio output taken from the
output pin 103'-7 of device 103,' is provided at output terminal 60.
Referring again to the encoder of FIG. 7, capacitor 208 is a DC blocking
capacitor. Resistor 315 provides a ground reference for the output
coupling capacitor 208. Resistor 316 acts a stand-off resistor to isolate
operational amplifier 103 from the output. Resistors 319 and 320 form a
voltage divider to provide a +7.5 volt bias reference to pin 103-3 of
device 103. Capacitor 210 bypasses pin 103-3 to ground.
In this practical implementation of the preferred embodiment, amplifier 102
preferably is one of two dual variable operational amplifiers contained on
the RCA CA3280 integrated circuit chip. One of the two variable amplifiers
may be used for the encoder while the other is used for the decoder. Such
an arrangement is particularly useful when the encoder and decoder of the
present invention are used, for example, in the same physical package to
provide the digital signal for a digital delay line. In other
applications, where the encoder and decoder are not on the same circuit
board and do not share devices on the same integrated circuit chip,
well-known component matching and temperature compensation techniques will
likely be required. Also, the application and packaging of the practical
implementation allows the use of a very high clock rate, in the order of 1
to 2 MHz. However, such a high clock rate is not critical to the
invention.
The above mentioned feedback loop around the variable-gain integrator (from
pin 103-1 of device 103 to the positive input pin 102-16 of device 102)
that causes it to operate as a variable-frequency filter includes resistor
305. Capacitor 201 in parallel with the resistance of the internal
linearizing diodes of amplifier 102 determines the pole of the low-pass
shelving filter (corresponding to the break frequency f.sub.1 of filter 16
of FIG. 1) and the combination of resistor 307 and capacitor 202 determine
the zero (corresponding to the break frequency f.sub.2 of filter 16). The
resistance of the internal linearizing diodes of amplifier 102 is much
smaller than the value of resistors 301 and 302. It is recognized that the
pole determined by the internal linearizing diodes of amplifier 102 and
capacitor 201 varies with signal level and temperature; however, in the
practical implementation where the encoder and decoder are on the same
printed circuit board and use two halves of the same integrated circuit
device, there is very close tracking. In other applications, as mentioned
above, additional component matching and temperature compensation may be
necessary, using well-known techniques.
With very high clock rates in the order of 1 to 2 MHz, the zero
(corresponding to the break frequency f.sub.2 of filter 16) of the
low-pass shelving network just described may be located above the audio
spectrum, a zero frequency of about 20 to 30 kHz in this practical
embodiment, allowing the full effect of the pre- and de-emphasis to be
obtained. At lower clock rates, the zero must be moved down in frequency
in order to keep the system stable.
Although the exact break frequency is not critical, in the practical
implementation of the preferred embodiment, 6 kHz was chosen as the pole
frequency (the lower break frequency, corresponding to f.sub.1 of filter
16 in FIG. 1) of the pre and de-emphasis/noise shaping shelving network
because it provides a reasonable compromise between adaptation range and
signal handling capability. The rationale behind the choice of 6 kHz is
based on the recognition that the spectral envelope of most music is such
that, on the average, low-frequency components of music are at a higher
level than high-frequency components and the components approximately
follow a curve that rolls off at a 25 microsecond rate--a single-pole
rolloff at 6 kHz. Thus, a pre-emphasis curve with a single pole at 6 kHz
"pre-whitens" the music signal: it pushes up high-frequency components so
that the resulting signal has approximately a white (flat) spectral
balance. Although the pre-emphasis would appear to increase the
probability of overload at high frequencies, this tends not to occur
because most music does not contain high-level high-frequency components
that would overload the system even after pre-emphasis.
In the practical embodiment, the variable-frequency low-pass filter has a
corner frequency that approaches 6 kHz as a theoretical limit. Thus, the
overall effect of that variable filter in cascade with the
pre-emphasis/de-emphasis shelving network is a 2-pole roll off at
frequencies above 6 kHz. While the 2-pole rolloff provides a much better
reduction in high-frequency noise modulation than does a single-pole roll
off, it does adversely affect the high-frequency overload capability.
However, this can be recovered by sacrificing some of the dynamic range,
which is much more than adequate. The practical implementation of the
invention has a dynamic range in excess of about 110 dB, thus allowing the
high-frequency overload capability of a single-pole pre-emphasis to be
regained by reducing the nominal input level to the circuit by the same
amount as the additional boost at the top end of the audio spectrum (15
kHz); about 8 dB.
The feedback path including resistor 305 alters the mode of operation of
the circuit, turning the variable-gain integrator into a
variable-frequency integrator; without that feedback path the circuit
would act as a conventional variable step-size delta modulator with
additional noise shaping provided by the low-pass shelving network.
The turnover frequency at which the variable-frequency integrator switches
from a delta modulator to a delta-sigma modulator changes with the
adaptation control signal. The effect of capacitor 202 in the feedback
path of operational amplifier 103 in cooperation with feedback applied
around devices 102 and 103 provides the pole that forms the
variable-frequency leaky integrator. Feedback applied around this network
limits the low-frequency gain to a fixed value: at low frequencies when
the loop gain through resistor 305, amplifier 102, and amplifier 103 is
larger than unity, the frequency response is flat as determined by
feedback resistor 305. At high frequencies when the loop gain falls below
unity, the overall gain is essentially the open-loop gain because the
contribution of resistor 305 becomes negligible. In that way, the result
is a low-frequency pole that changes in frequency because the
low-frequency gain remains constant and the amount of forward gain
changes. The point at which the fixed gain caused by feedback intersects
the changing open-loop gain causes the pole to move as the forward gain
changes.
In this practical implementation of the preferred embodiment, the range of
adaptation of the filter is limited such that the highest frequency that
the filter can attain is approximately equal to the pole frequency of the
shelving network. This provides a reasonable compromise between adaptation
range and signal handling capability. If the pole frequency of the
shelving network were lowered, then the maximum signal level curve would
move down in frequency, thereby reducing the high-frequency signal
handling capability relative to lower frequencies.
The circuit operates so that, on a steady-state basis, the
variable-frequency filter corner frequency substantially matches the
frequency of an applied sine wave at a maximum amplitude level. If the
applied sine wave has an amplitude level less than the maximum level for
which the circuit parameters are chosen, the filter corner frequency does
not fully shift to the frequency of the sine wave but is lower in
frequency; the filter adopts a corner frequency lower than the sine-wave
frequency in order to provide sufficient encoder gain at the sine-wave
frequency to maintain proper bit-stream loading.
A further advantage of this arrangement is the substantial elimination of
audible "thumps" that occur in prior art variable step-size delta
modulators, including not only those that use variable-gain integrators
but also those in which pulse height is modulated. For example, in the
arrangement of the present invention, the gain does not change at low
frequencies and at DC; thus, there is no changing amplification of input
offsets of a voltage-controlled element as there is in prior art
variable-gain integrator type delta modulators. The circuit of the present
invention may be built without any offset trims at the variable amplifier
102.
Referring again to FIG. 7, D flip-flop 101 receives the output of
comparator 106 at its D input 101-2. In the decoder, D flip-flop 101'
receives the digital input signal applied to terminal 56 at its D input
101'-12. Both flip-flops receive clock inputs from terminals 58 and 58' at
their respective clock inputs 101-3 and 101'-11 As mentioned above, clock
rates of about 1 to 2 MHz are suitable when the encoder and decoder are
used in the environment of a digital audio delay line. However, much lower
clock rates are usable for many applications and the clock rate is not
critical to the invention. In this practical embodiment, both the encoder
and decoder flip-flops 101 and 101' may be contained on a single
integrated circuit chip, such as the 74HC74.
The adaptation control-signal generator circuit receives as inputs the
digital bit stream from the true (Q) output 101-5 of flip-flop 101 (101'-9
in the decoder) and also the opposite polarity of that bit stream from the
complement (not Q) output 101-6 (101'-8 in the decoder). In the encoder,
the true (Q) output of flip-flop 101 provides the encoder digital output
to output terminal 52. In both the encoder and decoder, the Q output bit
stream is applied, along with the not Q output bit stream to respective RC
low-pass filters, formed by resistor 308/capacitor 203, and resistor
309/capacitor 204. The corner frequency of the respective single-pole
low-pass filters is at or somewhat above the upper limit of the audio band
handled by the overall system. The low pass filters filter out the clock
signal component to provide outputs that are continuous analog
representing the two polarities of the audio content of the digital bit
stream. In applications where a lower clock rate is used, it may be
desirable to use second-order low-pass filters.
In this practical embodiment, the D flip-flops 101 and 101' are contained
in the 74HC74 which is a CMOS device that provides +5 volts as its "1"
output and ground as its "0" output; +5 volts is applied to the R and S
inputs (101-1/101'-13 and 101-4 and 101'-10, respectively) of the encoder
and decoder flip-flops 101 and 101'. Because the flip-flop outputs are
used as analog signals, resistor 326 in series with the supply and
capacitor 209 bypassed to ground are used to filter noise from the power
source. When the digital output is a "1" the input to the resistor
309/capacitor 204 low-pass filter is +5 volts and the input to the other
low-pass filter is at ground potential; when the digital output is "0,"
the situation is reversed. A main filter corner frequency of about 23 kHz
is used in this practical implementation which is intended to handle audio
input signals as high as about 15 kHz.
Emitter-follower buffer transistors 401 and 402 each function as a
half-wave rectifier, and thus, because the phase of the signal fed to one
transistor is opposite to the phase of the signal fed to the other, the
two transistors act together as a full-wave rectifier. The full-wave
rectified signal from the emitters of transistors 401 and 402 feeds a fast
attack/slow decay smoothing circuit (charging resistor 310, capacitor 206,
and discharging resistor 311) which in turn feeds common base buffer
transistor 403.
The operation of this arrangement is best understood by way of example.
Transistors 401 and 402, of course, will conduct when forward biased (base
voltage exceeds emitter voltage) and will be cut off when reverse biased.
Their respective emitter voltages are determined by the charge on
smoothing capacitor 206. Buffers 401 and 402 charge capacitor 206 through
resistor 310, in the manner of charging a capacitor through a diode.
Capacitor 206 discharges only through resistor 311, which has a higher
resistance than resistor 310; thus, it is a fast attack, slow decay
circuit. In a practical implementation of | | |
