In the digital signal processor used for realizing application filters, the filter output calculation processing system 5 and the tap coefficient update calculation processing system 6 are separated. In the update calculation processing system 6, the integrating calculation for the tap coefficient updating that requires read and write operations on the data memory DRM is performed in one machine cycle by using the dedicated data bus 10 and executing the read-modify-write operation on the data memory. As a result, to the extent that the time taken by the integrating processing which has conventionally required two machine cycles can be shortened, the operation clock frequency can be lowered to reduce the power consumption while maintaining the processing capability per unit of time.

A multiplication system performs a series of multiplications and accumulations of plural pairs of first and second operands. The system includes first and second buses, a memory for storing the plural pairs of first and second operands, and a read buffer coupled to the memory for sequentially reading the first and second operands. An accumulator coupled to the first bus receives the first operands from the read buffer and stores the first operands. A multiplier, coupled to the first and second buses, receives the first and second operands in parallel over the first and second buses respectively from the accumulator and the read buffer respectively to provide a series of products. The system further includes an accumulator for accumulating the products to provide a final accumulated product.

In a packet communication system, the delay time needed in a jitter buffer is determined, enabling a smooth data feed to an application without excessive delays, by methods and apparatus that vary the size of the jitter buffer based on an estimated variation of packet transmission delay derived from the times of arrival of stored packets. A variance buffer stores variances of the times of arrival of stored packets, and the estimated variation of packet transmission delay is derived from the stored variances. The size of the jitter buffer can be changed preferentially during periods of discontinuous packet transmission.

An integrated circuit processor architecture that implements digital signal processing (DSP) functions with less hardware, improved speed and a more efficient layout. The central processing unit (CPU) resources are used in conjunction with an integrated multiply/accumulate unit to perform DSP operations. Use of the CPU's internal register for the circular buffer of the DSP multiply/accumulate function allows a minimum amount of lower speed hardware to be used for the multiply/accumulate unit and permits DSP operations to be performed in parallel. The multiply/accumulate unit takes advantage of the inherent accumulating properties of conventional multiplier designs to perform multiplication of two signed binary numbers using the modified Booth's algorithm but in both reduced cycle time and hardware requirements. This is accomplished by using the adder within the multiplier to sum the product terms. Instead of clearing the adder of the result of one multiplication before beginning another, the result is maintained and all subsequent partial products are added to it to generate a final output. The placement of the 32-bits of the multiply/accumulate unit's multiplicand register is arranged in two rows of 8 even bits and two rows of 8 odd bits to allow left shift by two with a single loop around and to provide direct interface with the 16-bit data latch register on its input and the rest of the 32-bit arithmetic logic unit (ALU) on its output.

An arithmetic processing unit which speeds up arithmetic operations performed up on vectors, matrices or a vector and a matrix, and is coupled to a central processing unit. The arithmetic unit includes a program memory for storing a microprogram corresponding to a macro-instruction code fed from the central processing unit, wherein each macro-instruction is representative of an arithmetic operation. Within the arithmetic unit, operand codes are transferred from an internal register array to operand registers assigned to an augend and an addend, or a multiplicand and a multiplier for calculations carried out by an arithmetic and logic unit. The operand codes for the arithmetic operation are successively transferred to the internal register array prior to the execution of the macro-instruction codes, so that the arithmetic processing unit completes each task without the need for interruptions to receive operands.