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Claims  |
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What is claimed is:
1. A semiconductor memory device comprising:
a plurality of bit lines and a plurality of word lines disposed
perpendicular to one another on a semiconductor substrate;
a plurality of dynamic memory cells disposed at intersections of said bit
lines and said word lines;
equalizer means connected to said bit lines;
sense amplifier means connected to said bit lines;
latch means connected to said bit lines; and
means, for, when a row address strobe signal for loading a row address into
the memory device is active during a read cycle, selecting a word line,
causing said latch means to latch data read from memory cells connected to
the selected word line, then ceasing the selection of said word line, and
causing said equalizer means to preset a level of the bit lines.
2. A semiconductor memory device according to claim 1, wherein said latch
means is a static memory cell consisting of a flip-flop, said static
memory cell being connected to a corresponding bit line via a first
transfer gate and to an input/output line via a second transfer gate;
wherein said first transfer gate is rendered conductive for a fixed time
after the word line selection and said second transfer gate is rendered
conductive by a column select signal selected when a column address strobe
signal for loading a column address signal into the semiconductor memory
device is active.
3. A semiconductor memory device according to claim 1, wherein said sense
amplifier means is used as said latch means, and said sense amplifier
means is a flop-flop connected to a corresponding bit line via a first
transfer gate and to an input/output line via a second transfer gate,
wherein said first transfer gate being rendered conductive for a fixed
time after the word line selection, and said second transfer gate being
rendered conductive by a column select signal selected when a column
address strobe signal for loading a column address signal into the
semiconductor memory device is active.
4. A semiconductor memory device according to claim 1, further comprising:
means for serially accessing memory cell data latched into said latch means
during the row address strobe signal's active period, by changing the
level of the column address strobe signal for loading the column address
signal into the semiconductor memory device.
5. A semiconductor memory device according to claim 1, wherein each of said
bit lines comprises a plurality of divided bit lines to which a plurality
of memory cells are connected and a main bit line to which said divided
bit lines are connected via select gates; said sense amplifier means
comprises divided bit line sense amplifiers each provided for each of said
divided bit lines; and said latch means is connected to said main bit
lines via first transfer gates which are rendered conductive after the
word line selection and connected to input/output lines via second
transfer gates which are rendered conductive by a column select signal
selected when a column address strobe signal for loading a column address
signal into the semiconductor memory device is active.
6. A semiconductor memory device according to claim 5, further comprising:
means for preventing the potential of said main bit lines from becoming a
power source potential when data in a memory cell is transferred from a
divided bit line to said latch means via said main bit line.
7. A semiconductor memory device according to claim 5, further comprising:
means for serially accessing memory cell data latched into said latch means
during the row address strobe signal's active time period by changing the
level of the column address strobe signal for loading the column address
signal into the semiconductor memory device.
8. A semiconductor memory device according to claim 5, in which, in a read
mode of operation, the row address strobe signal becomes active, the
column address strobe signal becomes active, a signal informing that the
row address has been loaded becomes active and a column address-buffer
control signal is generated and, in a write mode of operation, the column
address strobe signal becomes active, the row address strobe signal
becomes active, a signal informing that the column address has been loaded
becomes active, and a row address-buffer control signal is generated.
9. A semiconductor memory device according to claim 1, wherein an address
multiplexing system is used in which a column address for selecting a bit
line and a row address for selecting a word line are entered into said
memory device via the same address terminals thereof, and wherein, both in
a read cycle and in a write cycle, a column address is loaded by the
column address strobe signal and then a row address is loaded by the row
address strobe signal.
10. A semiconductor memory device comprising:
a plurality of bit lines and a plurality of word lines disposed
perpendicular to one another on a semiconductor substrate;
a plurality of dynamic memory cells disposed at intersections of said bit
lines and said word lines; and
plural latch means connected to said bit lines for precharging said bit
lines during a row address strobe signal's active period, each of said
latch means being connected to a pair of write nodes via a write transfer
gate, each of said pair of write nodes being connected to the bit lines
via a first transfer gate pair and to an input/output line via a second
transfer gate.
11. A semiconductor memory device according to claim 10, wherein, in a read
cycle, the row address strobe signal for loading the row address signal
into the semiconductor memory device is rendered active prior to a column
address strobe signal for loading a column address signal into the
semiconductor memory device so that a row address is loaded prior to a
column address, and wherein, in a write cycle, the column address strobe
signal is rendered active prior to the row address strobe signal so that a
column address is loaded prior to a row address.
12. A semiconductor memory device according to claim 10, wherein, when the
row address strobe signal for loading a row address signal into the
semiconductor memory device is active in a read cycle, a word line is
selected, the selection of the word line is ceased after data in memory
cells connected to the word line is latched into said latch means, and the
bit line is precharged by an equalizer; and, when after the row address
strobe signal becomes nonactive and a column address strobe signal for
loading a column address signal into the semiconductor memory device is
active, when a column is selected, data in a sense amplifier is read out
onto said input/output line irrespective of the precharging of said bit
line.
13. A semiconductor memory device according to claim 10, wherein, when a
column address strobe signal for loading a column address signal into the
semiconductor memory device is active in a write cycle, when a write
enable signal is rendered active, a column address is loaded, said write
transfer gate is turned off, a column select line is selected by the
column address, and data on said input/output line is transferred to said
bit line via said first and second transfer gate; and when the row address
strobe signal for loading a row address signal into the semiconductor
memory device is active, a word line is selected by a row address, data on
said bit line is written into a selected memory cell, said write transfer
gate is turned on to connect said latch means to said bit line, rewrite
said selected memory cell, reset said word line and precharge said bit
line.
14. A semiconductor memory device according to claim 10, wherein said latch
means is a static memory cell consisting of a flip-flop.
15. A semiconductor device according to claim 10, further comprising a
sense amplifier which is used for each of said latch means.
16. A semiconductor memory device according to claim 10, further
comprising:
means for serially accessing memory cell data latched into said latch means
when the row address strobe signal is active, by changing the level of the
column address strobe signal.
17. A semiconductor memory device according to claim 10, wherein each of
said bit lines comprises a plurality of divided bit lines to which a
plurality of memory cells are connected and a main bit line to which said
divided bit lines are connected via select gates; said sense amplifier
comprises a divided bit line sense amplifier provided for each of said
divided bit lines; and said latch means is connected to said main bit line
via a first transfer gate which is rendered conductive after the word line
selection and connected to input/output lines via a second transfer gate
which is rendered conductive by a column select signal selected when a
column address strobe signal for loading a column address signal into the
semiconductor memory device is active.
18. A semiconductor memory device according to claim 17, further
comprising:
means for preventing the potential of said main bit lines from becoming a
power source potential when data in said memory cell is transferred from a
divided bit line to said latch means via said main bit line.
19. A semiconductor memory device according to claim 17, further
comprising:
means for serially accessing memory cell data latched into said latch means
when the row address strobe signal is active, by changing the level of the
column address strobe signal.
20. A semiconductor memory device according to claim 17, in which, in a
read mode of operation, the row address strobe signal becomes active, the
column address strobe signal becomes active, a signal informing that the
row address has been loaded becomes active, and a column address-buffer
control signal is generated and, in a write mode of operation, the column
address strobe signal becomes active, the row address strobe signal
becomes active, a signal informing that the column address has been loaded
becomes active, and a row address-buffer control signal is generated.
21. A semiconductor memory device comprising:
a plurality of bit lines and a plurality of word lines disposed
perpendicular to one another on a semiconductor substrate;
a plurality of dynamic memory cells disposed at intersections of said bit
lines and said word lines;
means, connected to said bit lines, for presetting an initial level of the
bit lines;
sense amplifier means connected to said bit lines;
latch means connected to said bit lines; and means for, when a row address
strobe signal for loading a row address into the memory device is active
during a read cycle, selecting a word line, causing said latch means to
latch data read from memory cells connected to the selected word line,
then ceasing the selection of said word line, and causing said presetting
means to preset the initial level of the bit lines. |
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Claims |
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Description |
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BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated semiconductor memories using
dynamic RAMs (dRAMs) containing dynamic memory cells for destructive
readout.
2. Description of the Related Art
Recently many inventions and developments have been made to speed up
semiconductor memories. The semiconductor memories include dRAMs and sRAMs
(static RAMs). The dRAMs are superior to the sRAMs in storage capacity and
cost, but inferior in speed. The reason why the dRAMs are inferior to the
sRAMs in speed is that the dRAMs are increased in integration density by
the use of an address multiplexing method in order to decrease their cost
per bit. The fact that dRAMs need refreshing and bit-line precharging
because they are of destructive-read type may also be attributed to their
low-speed operation. With computers using the sRAMs as their main
memories, their machine cycle is determined only by an access time to the
sRAM. Where the dRAMs are used as main memories, the machine cycle is
determined by their access time and bit-line precharging time.
For that reason, in the conventional dRAMs, various operation modes, such
as a page mode, a nibble mode and a static column mode, have been
developed to shorten the access time.
However, a problem with the conventional dRAMs is that, even if the access
time is reduced in a normal access mode, the cycle time is not so reduced.
For example, with a 1M-bit dRAM having an access time of 100 nsec in the
normal access mode, the cycle time is 190 nsec in its specification
because it is a sum of an active time and the precharging time. Even if
the access time is reduced by half, the cycle time will not be halved
unless the precharging time is also reduced by half. The difficulty in
reducing the precharging time is due not only to the fact that the
capacitive loads of bit lines to be charged have been increased to
increase the storage capacity of the dRAMs, but also to the fact that the
bit lines are precharged and equalized during a precharging period in
which an RAS signal (row address strobe signal for loading the row address
into the memory device) goes from a logic "0" to a logic "1", not during
an active period to read or write data.
Where semiconductor memories are installed in computers, the length of
machine cycle is an important factor in the performance of the computers.
In the static RAMs, since the access time and the cycle time coincide with
each other, the reduction of the access time will also reduce the machine
cycle. In the dynamic RAMs, however, the reduction of the access time
alone will not lead to the reduction of the machine cycle.
In the conventional dRAMs of address multiplexing type, there is no
distinction between a read cycle and a write cycle because an address data
selector is controlled by a CAS signal (column address strobe for loading
the column address into the memory device) only. That is, during an active
cycle, a row address strobe (RAS) is input into the dRAM prior to the CAS.
The row address and the column address are issued in this sequence from
the address data selector and then entered into a dRAM chip. To secure
operational margin surely, a certain time is needed from when the RAS is
made active until the CAS is made active. It is thus difficult to shorten
the cycle time of the dRAMs and hence the machine cycle of computers using
the dRAMs.
As described above, the conventional dRAMs have a problem that the
reduction of the access time does not lead to the reduction of the cycle
time, and thus the machine cycle of the computers using the dRAMs cannot
be reduced.
SUMMARY OF THE INVENTION
It is a first object of the present invention to provide a semiconductor
memory using a dRAM which saves the need for a precharging time for bit
lines, which is conventionally separate from an access time, and thus
reduces its cycle time.
It is a second object of the present invention to provide a dRAM
semiconductor memory of address-multiplexing type which enables a
high-speed write operation.
It is a third object of the present invention to provide a dRAM
semiconductor memory with divided bit-line structure which saves the need
for a precharging time for bit lines and thus reduces its cycle time.
The first object is achieved by connecting a latch means to bit lines and
initiating precharging of the bit lines after, during a RAS active time
period, data is transferred from a memory cell connected to a selected
word line to the latch means via the bit lines.
The second object is achieved by, in an address multiplexing dRAM
semiconductor memory, loading a column address first by inputting a CAS,
and then a row address by inputting a RAS in both a read cycle and a write
cycle and writing data into a bit line pair or a circuit immediately
preceding the bit line pair during the write cycle.
The third object is achieved by, in a dRAM semiconductor memory of a
divided bit-line configuration, connecting a latch means between main bit
lines and input/output lines and transferring data between the dRAM and
the outside while precharging the main bit lines and sub bit lines.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a semiconductor memory device according to a
first embodiment of the present invention;
FIG. 2 is a circuit diagram of a portion of the first embodiment;
FIGS. 3A and 3B show waveforms of signals indicating the operation in a
readout cycle of the first embodiment;
FIG. 4 shows a first modification of a latch-type memory cell of the first
embodiment;
FIG. 5 shows a second modification of the latch-type memory cell of the
first embodiment;
FIG. 6 shows a third modification of the latch-memory cell of the first
embodiment;
FIG. 7 shows a fourth modification of the latch-type memory cell of the
first embodiment;
FIG. 8 is a block diagram of a semiconductor memory according to a second
embodiment of the present invention;
FIGS. 9A, 9B, and 9C show waveforms of signals indicating an operation in a
readout cycle of the second embodiment;
FIGS. 10A, 10B, 10C, and 10D show waveforms of signals indicating the
operation in a write cycle of the second embodiment;
FIGS. 11A and 11B show waveforms of signals indicating the operation in a
readout cycle of a third embodiment;
FIGS. 12A and 12B show waveforms of signals indicating the operation in a
write cycle of the third embodiment;
FIG. 13 is a block diagram of a semiconductor memory according to a fourth
embodiment of the present invention;
FIG. 14 is a circuit diagram of a portion of the fourth embodiment;
FIGS. 15A and 15B show waveforms of signals indicating the operation in a
readout cycle of the fourth embodiment;
FIGS. 16A and 16B show waveforms of signals indicating the operation in a
write cycle of the fourth embodiment;
FIGS. 17A and 17B are a block diagram of a semiconductor memory according
to a fifth embodiment of the present invention;
FIG. 18 is a circuit diagram of a portion of the fifth embodiment;
FIGS. 19A and 19B show waveforms of signals indicating the operation in a
readout cycle of the fifth embodiment;
FIGS. 20A and 20B are a block diagram of a semiconductor memory according
to a sixth embodiment of the present invention;
FIG. 21 is a circuit diagram of a portion of the sixth embodiment;
FIGS. 22A and 22B show waveforms of signals indicating the operation in a
readout cycle of the sixth embodiment; and
FIGS. 23A and 23B show waveforms of signals indicating the operation in a
write cycle of the sixth embodiment.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring now to FIG. 1, there is shown the overall structure of a first
embodiment of the present invention. Over a semiconductor substrate not
shown, plural pairs of bit lines BLi, BLi (i=1.about.m) and plural word
lines MWj (j=1.about.n) are disposed perpendicular to each other and dRAM
cells MCij are placed at their intersections. Each dRAM cell MCij is
selectively driven by word line MWj so that data is transferred between
bit lines BLi and BLi. In addition to the dRAM cells, dummy cells DCi1 and
DCi2 are coupled to bit-line pair BLi and BLi of each row. Dummy cells
DCi1 and DCi2 are driven by dummy word lines DW1 and DW2, respectively.
A bit-line sense amplifier 10-i is coupled to ends of bit lines BLi, BLi
for each of rows in order to detect the level of data read out onto BLi
and BLi.
To equalize and precharge bit lines BLi, BLi, an equalizer 50-i is coupled
to sense amplifier 10-i. Equalizer 50-i is connected with a bit-line
precharging power supply VBL and also supplied with an equalizing signal
EQL1.
The other ends of bit lines BLi, BLi are coupled to a latch type memory
cell (hereinafter, is called as latch memory cell) 20-i via a first
transfer gate 30-i which is supplied with a control signal .phi.T. Latch
memory cell 20-i is supplied with activation signals .phi.CE and .phi.CE.
Outputs of latch memory cell 20-i are coupled to input/output lines I/O
and I/O via a second transfer gate 40-i which is supplied with a column
select signal CSLi.
FIG. 2 shows a specific arrangement of the dRAM of FIG. 1, particularly a
detailed circuit diagram for one row. The dRAM cell MC and dummy cell DC
are of a well known type comprised of one transistor and one capacitor. A
reference potential terminal of the capacitor is connected to a plate
power supply VPL. Dummy cells DCi1 and DCi2 include n channel MOS
transistors Q9 and Q10, respectively, which are connected to a precharging
power supply VDC, for data-writing.
Bit line amplifier 10-i is comprised of a pair of n channel MOS transistors
Q4 and Q5 and another pair of p channel MOS transistors Q6 and Q7.
Activation signals .phi.SE and .phi.SE applied are to the respective pairs
of Q4, Q5 and Q7, Q8 at their sources connected in common.
Equalizer 50-i is comprised of three n-channel MOS transistors Q1, Q2, Q3
which are supplied at their gates with equalize signal EQL1. Transistors
Q1 and Q2 are adapted for precharging and have their sources connected to
bit lines BLi and BLi, respectively, with their drains connected to
precharging power supply VBL in common. Transistor Q3 is adapted for
equalizing and have its source and drain connected to bit lines BLi and
BLi, respectively.
Latch memory cell 20-i includes a flip-flop comprised of a pair of n
channel MOS transistors Q18 and Q19 and a flip-flop comprised of a pair of
p channel MOS transistors Q21 and Q22. Activation signals .phi.CE and
.phi.CE, acting as latch clocks, are applied to the common source
connections of the transistor pairs, respectively. Q20 is an n-channel MOS
transistor used for equalizing.
Nodes Ai and Ai of latch memory cell 20-i described above are coupled to
bit lines BLi, BLi via n channel MOS transistors Q16 and Q17,
respectively, which form first transfer gate 30-i. On the other hand,
nodes Ai and Ai are also coupled to input/output lines I/O and IO via n
channel MOS transistors Q23 and Q24, respectively, which form second
transfer gate 40-i. First transfer gate 30-i is controlled by control
signal .phi.T, while second transfer gate 40-i is controlled by column
select signal CSLi selected by a column address.
The operation of the dRAM with such an arrangement as described above will
be described hereinafter.
FIGS. 3A and 3B are a timing diagram showing the operation during a read
cycle. Here, an operation, in a system in which bit lines BLi and BLi are
precharged to (1/2) VDD, for transferring data in latch memory cell 20-i
to input/output lines I/O and I/O will be indicated.
In the beginning of operation, since bit-line equalize signal EQL1 is at
the VDD level and precharging power supply VBL provides (1/2) VDD volts,
all of the bit lines BL and BL are precharged to (1/2) VDD. Assume now
that VDD (logic "1") is written into a node N1 between capacitor C3 and
transistor Q12 of dRAM cell MCi1 associated with the i-th bit lines BLi
and BLi. Furthermore, assume that a node N3 between capacitor C2 and
transistor Q11 of dummy cell DCi2 is initially set to (1/2) VDD level by
write power supply VDC.
When the RAS goes from logic "1" level (VIH) to logic "0" level (VIL), the
operation goes into an RAS active mode. As a result, equalize signals EQL1
and EQL2 go from VDD volts down to VSS volts so that bit lines BLi and BLi
are electrically disconnected from each other, and node N3 of dummy cell
DCi2 assumes a floating state.
Subsequently, for example, when word line MW1 is selected and this line and
dummy word line DW2 are raised to (3/2) VDD level, the stored data in dRAM
cell MCi1 and dummy cell DCi2 are read out onto bit lines BLi and BLi,
respectively. At the same time, equalize signal EQL3 of latch memory cell
20-i decreases from VDD volts to VSS volts.
Subsequently, n-channel transistor activation signal .phi.SE decreases from
(1/2) VDD volts to VSS volts, and then p-channel transistor activation
signal .phi.SE increases from (1/2) VDD volts to VDD volts. As a result,
bit line BLi onto which logic "1" data has been read out is raised to VDD,
while bit line BLi to which data in dummy cell DCi2 has been read out is
lowered to VSS.
Control signal .phi.T subsequently goes from VSS to VDD causing first
transfer gate 30-i to turn on. When activation signal .phi.CE goes from
(1/2) VDD to VSS and .phi.CE goes from (1/2) VDD to VDD, the contents of
bit lines BLi and BLi are transferred to nodes Ai and Ai of latch memory
20-i.
At a time when the data on bit lines BLi and BLi are thus transferred into
latch memory cell 20-i, if a write trigger signal WE generated outside the
dRAM chip is at logic "1" and hence the operation is in a read mode, then
the bit-line precharge will be initiated automatically. The precharge
operation will be described next.
After memory cell MCi1 selected for readout has sufficiently been restored
(rewritten), selected word line MWi1 and dummy word line DW2 are lowered
in potential from (3/2)VDD to VSS causing latch memory cell 20-i to be
electrically disconnected from bit lines BLi and BLi.
Bit-line equalize signal EQL1 goes from VSS to VDD causing equalizer 10 to
precharge the bit lines. In this case, when CAS clock goes from logic "1"
to logic "0", if the i-th column is selected, column select signal CSLi is
raised in level from VSS to VDD or (3/2) VDD causing second transfer gate
40-i to turn on and nodes Ai and Ai of latch memory cell 20-i to be
electrically connected to input/output lines I/O and I/O. When the i-th
column is selected, I/O remains at VDD, I/O is lowered from VDD to VSS,
and an output terminal Dout (not shown) connected to input/output lines
I/O and I/O goes from high-impedance level (Hiz) to logic "1" level (VOH).
If the column select signal CSLi goes to VDD when control signal .phi.T is
at VDD and first transfer gate 30-i in the on state, bit lines BLi and BLi
and nodes Ai and Ai of latch memory cell 20-i are simultaneously
electrically connected to input/output lines I/O and I/O, in which case
the data on bit lines BLi and BLi are directly read out onto input/output
lines I/O and I/O.
As described above, according to the present invention, by the provision of
a latch memory cell at ends of bit lines in order to temporally store data
read out of a dRAM cell, the bit lines can be precharged during a RAS
active time. That is, the latch memory cell, which enables data to be read
from or written into during a bit-line precharge time, is provided between
the paired bit lines and the input/output lines, and when the RAS goes
from logic "1" to logic "0", a word line is selected so that data in the
dRAM cell is transferred to the latch memory. In this case, if the CAS is
pulled down to logic "0" prior to the RAS, a column select line can be
selected to read out data to the outside immediately after the selection
of the word line. Thereafter by turning off the transfer gate between the
bit lines and the latch memory cell, the bit lines can be precharged while
the RAS remains at logic "0". In other words, precharging the bit lines
can be performed during a RAS active time, which has been performed in the
prior art during a RAS precharge time other than the RAS active time. As a
result, the cycle time can be shortened. This is very effective for
speeding up computers using large-capacity dRAMs as their main memories.
In the above embodiment, the precharged level of the bit lines is (1/2)
VDD. Alternatively, the precharged level may be VDD. BICMOS circuits
(circuits using a combination of bipolar transistors and CMOS transistors)
may be used in the sense amplifier and its peripheral circuits.
Furthermore, latch memory cell 20-i may be modified in various ways as
shown in FIGS. 4 through 7.
FIG. 4 shows a first modification of the latch memory cell 20-i which is
modified such that precharging n-channel MOS transistors Q25 and Q26 are
added. The drains of transistors Q25 and Q26 are connected together to
precharging power supply VLC. The transistors are controlled by equalize
signal EQL3 so that the nodes Ai and Ai of the latch memory cell 20-i are
initially set to VLC (e.g., (1/2) VDD). As precharging power supply VLC
the precharging power supply VBL for the bit lines may be used.
In a second modification of FIG. 5, p-channel MOS transistors Q21 and Q22
of the first embodiment are replaced with load resistances R1 and R2,
respectively, for connection to VDD. Resistances R1 and R2 may be formed
of polysilicon, for example. In this modification, the initial level of
activation signal .phi.CE is chosen to be VDD so that nodes Ai and Ai are
initially set to the VDD level.
FIG. 6 shows a third modification which uses n-channel MOS transistors Q27
and Q28 in place of resistances R1 and R2 of FIG. 5. In this case,
transistors Q27 and Q28 are of enhancement type and each act as a load
with drain and gate connected together. As a result, the initial level of
nodes Ai and Ai will be set to VDD-Vth. Vth stands for the threshold
voltage of Q27, Q28.
FIG. 7 shows a fourth modification which uses n-channel MOS transistors Q29
and Q30 of depletion type as loads. In this case, transistors Q29 and Q30
each have its gate connected to its source. In this arrangement, the
initial level of nodes Ai and Ai will be set to VDD.
A second embodiment of the present invention will be described next. The
second embodiment is arranged to precharge, like the first embodiment, bit
lines in an address-multiplexing type dRAM. That is, a read cycle and a
write cycle are made different from each other in the input sequence of an
row address and a column address. The overall block diagram is shown in
FIG. 8. The arrangement of the dRAM is the same as that in the first
embodiment and thus the description thereof is considered to be
unnecessary.
Referring to FIG. 8, an address data selector 170 is connected between a
dRAM chip 160 and a CPU 180. Address data applied from CPU 180 to address
data selector 170 has 2n bits. The n high-order bits of the address data
are used as a column address and the n low-order bits as a row address.
Address data selector 170 in turn applies the column address and the row
address to address inputs A1-An of dRAM chip 160.
Address data selector 170 has a select control terminal SEL adapted to
determine which of the column address and the row address is to be output
first. The level of a signal applied to select control terminal SEL is
determined by a gate circuit 190 according to a combination of levels of
RAS, CAS and WE. When among RAS, CAS and WE, RAS first goes from logic "1"
to logic "0", gate circuit 190 applies a signal of logic "1" to control
terminal SEL. When control terminal SEL is at logic "1" level, address
data selector 170 issues the row address first. After that, CAS goes to
logic "0" level causing control terminal SEL to go to logic "0" level. As
a result, the column address is issued from address data selector 170. The
above relates to a read cycle.
For a write cycle, on the other hand, CAS and WE go to logic "0" level
prior to RAS and thus the control signal from gate circuit 190 goes to
logic "0", causing the column address to be issued first. Subsequently,
RAS goes to logic "0" level, causing the row address to be issued from
address data selector 170.
It is to be noted here that delay circuits D1 and D2 are connected to RAS
and CAS input terminals, respectively, of dRAM chip 160. This is to
provide a setup time for an input address to dRAM chip 160.
The operation of the dRAM of the second embodiment described above will be
described hereinafter.
Referring to FIGS. 9A, 9B, and 9C, there are shown timing diagrams of the
operation during a read cycle. As in the first embodiment, the operation,
in the system where bit lines BL and BL are precharged to (1/2) VDD, to
transfer the data in latch memory 20-i onto input/output lines I/O, I/O
while the bit lines are being precharged is here shown. However, unlike
the first embodiment, data is transferred serially.
In the beginning of operation, since equalize signal EQL1 is at the VDD
level and bit-line precharging power supply VBL is at the (1/2) VDD level,
all the bit lines BL and BL have been precharged to (1/2) VDD. Assume now
that a logic "1" (VDD) is written into storage node N1 of dRAM cell MCi1
associated with i-th bit lines BLi and BLi of interest and storage node N3
of dummy cell DCi2 is initially set to (1/2) VDD by write power supply
VDC.
When the RAS goes from logic "1" level (VIH) to logic "0" level (VIL), the
operation goes into an RAS active mode. As a result, equalize signals EQL1
and EQL2 go from VDD volts down to VSS volts so that bit lines BLi and BLi
are electrically disconnected from each other, and node N3 of dummy cell
DCi2 assumes a floating state.
Subsequently, for example, when word line MWl is selected and this line and
dummy word line are raised to (3/2) VDD level, the stored data in dRAM
cell MCi1 and dummy cell DCi2 are read out onto bit lines BLi and BLi,
respectively. Thereafter, equalize signal EQL3 of latch memory cell 20-i
decreases from VDD volts to VSS volts.
Subsequently, n-channel transistor activation signal .phi.SE decreases from
(1/2) VDD volts to VSS volts, and then p-channel transistor activation
signal .phi.SE goes from (1/2) VDD to VDD. As a result, bit line BLi onto
which logic "1" data has been read out is raised to VDD, while bit line
BLi to which data in dummy cell DCi2 has been read out is lowered to VSS.
Subsequently, control signal .phi.T goes from VSS to VDD causing first
transfer gate 30-i to turn on. When activation signal .phi.CE goes from
(1/2) VDD to VSS and .phi.CE goes from (1/2) VDD to VDD, the contents of
bit lines BLi and BLi are transferred to nodes Ai and Ai of latch memory
20-i.
At a time when the data on bit lines BLi and BLi are thus transferred into
latch memory cell 20-i, if the write trigger signal WE generated outside
the dRAM chip is at logic "1" and hence in a read mode, then the bit-line
precharge will be initiated automatically. The precharge operation will be
described next.
After memory cell MCi1 selected for readout has sufficiently been restored
(rewritten), selected word line MWi1 and dummy word line DW2 are lowered
in potential from (3/2) VDD to VSS so that MCi1 goes into a nonselected
state. Afterward latch memory cell 20-i is electrically disconnected from
bit lines BLi and BLi.
Bit-line equalize signal EQL1 goes from VSS to VDD causing equalizer 10-i
to to precharge the bit lines. In this case, when CAS clock goes from
logic "1" to logic "0", if the i-th column is selected, column select
signal CSLi is raised in level from VSS to VDD or (3/2) VDD causing second
transfer gate 40-i to turn on and nodes Ai and Ai of latch memory cell
20-i to be electrically connected to input/output lines I/O and I/O. When
the i-th column is selected, I/O remains at VDD, I/O is lowered from VDD
to VSS, and the output terminal Dout goes from high-impedance level (Hiz)
to logic "1" level (VOH). The operation described so far is the same as
that of the first embodiment.
Subsequently, when RAS is in the logic "0" state and CAS goes from logic
"0" back to logic "1", the data at output terminal Dout is reset to Hiz.
The data of sense amplifier 10-i is also reset and I/O, which has been
lowered to VSS, is also precharged to the VDD level like I/O. A column
address buffer and a column decoder are also reset, and column select
signal CSLi goes from VDD to VSS.
Afterward, when the j-th column address is entered and CAS again goes from
logic "1" to logic "0", the j-th column select line CSLj is selected. The
content in the j-th latch memory cell, which is logic "0" now, is read out
so that the output terminal Dout goes from Hiz to logic "0" (VOL).
Moreover, CAS is set from logic "0" to logic "1" to perform CAS
precharging, and then the k-th column address is entered to render CAS
active with the result that the data in the k-th latch memory cell, in
this case logic "1", is read out.
When RAS is raised from logic "0" to logic "1" and CAS is subsequently
raised from logic "0" to logic "1", equalize signal EQL3 goes from VSS to
VDD, resetting data in all the latch memory cells 20.
As is evident from the foregoing, according to the second embodiment,
during the read cycle, by temporally storing data read from a memory cell
in the latch memory cell and by toggling the CAS, the serial access can be
performed while the bit lines are precharged during the RAS active period.
The write-cycle operation will be described with reference to timing charts
of FIGS. 10A, 10B, 10C, and 10D. Unlike the read cycle, during the write
cycle, the CAS goes from logic "1" to logic "0" prior to the RAS. At the
same time, the WE also goes to logic "0". As a result, a column address is
first entered in the dRAM chip. For example, where the i-th column is
selected, the column select signal CSLi does not rise at this time, but
the column address is latched into the column decoder for selecting a
column select line. The writing circuitry operates to activate a sense
amplifier associated with the input/output lines I/O and I/O. In this case
the I/O goes from VDD to VSS, while the I/O remains at VDD.
Subsequently, when the RAS clock goes from logic "1" to logic "0", the
equalize signals EQL1, EQL2 and EQL3 go from VDD down to VSS with the
result that the bit lines BLi, BLi and the nodes Ai, Ai of the latch
memory cell go into the floating state.
When the level of word line MWi1 and dummy word line DWi2 is raised from
VSS to (3/2) VDD by the entered row address, column select signal CSLi is
raised from VSS to VDD by the column address which has already been
latched into the column decoder and the control signal .phi.T also goes
from VSS to VDD. Consequently, first and second transfer gates 30 and 40
are turned on, and bit lines BLi and BLi are thus electrically connected
to input/output lines I/O and I/O, respectively, so that bit line BLi is
lowered from (1/2) VDD to VSS and bit line BLi is raised from (1/2) VDD to
VDD.
Subsequently, the n-channel transistor activation signal .phi.SE for
bit-line sense amplifier 10-i and the activation signal .phi.CE for the
latch memory cell go from (1/2) VDD to VSS, and then the p-channel
transistor activation signal .phi.SE and the latch-memory activation
signal .phi.CE go from (1/2) VDD to VDD. As a result, writing data into
the selected memory cell and rewriting data into non-selected memory cells
are initiated. That is, since node N1 of the selected dRAM cell MCi1 and
node N3 of dummy memory cell DCi2 are electrically connected to bit lines
BLi and BLi, respectively, node N1 goes from VDD to VSS so that logic "0"
is written into it, and node N3 goes from (1/2) VDD to VDD.
Next, when RAS and WE are in the "0" state, the CAS goes from logic "0" to
logic "1", resetting output terminal Dout and the sense amplifier. Like
the I/O, the I/O, which has been lowered to VSS, is also precharged to
VDD. At the same time, the column address buffer and column decoder are
also reset, and the column select signal CSLi goes from VDD to VSS.
Afterward, when the j-th column address is entered and the CAS goes from
logic "1" to logic "0" again, the j-th column select line CSLj is
selected. At the same time, data is output to output terminal Dout and, if
input data is logic "1", then the "1" data is written into a selected
memory cell of the j-th column.
Moreover, like the above, by causing the CAS to go from logic "0" to logic
"1" to perform the CAS precharge, the column address buffer, column
decoder output terminal Dout and sense amplifier are reset.
When the k-th column address is entered and the CAS goes from logic "1" to
logic "0" to start the CAS active period, "0" data is written into a
selected memory in the k-th column. Then, when WE goes from logic "0" to
logic "1" while the RAS and CAS are at logic "0", word line MW1 and dummy
word line DW2 are lowered from (3/2) VDD to VSS, resulting in the
non-selected state. At almost the same time, control signal .phi.T is also
lowered from VDD to VSS so that first transfer gate 30-i is turned off and
thus the latch memory cell is electrically disconnected from the bit
lines. The bit-line equalize signal EQL1 then goes from VSS to VDD,
initiating the precharging of the bit lines. At the same time, equalize
signal EQL2 goes from VSS to VDD, writing the initial set level of (1/2)
VDD into the dummy cell.
By the WE being changed from logic "0" to logic "1", the write circuitry is
disabled and instead the read circuitry is enabled so that data in the
k-th latch memory cell is read out from output terminal Dout. In the
present case, since the logic "0" has been written, logic "0" is output.
As described above, according to the second embodiment utilizing the
arrangement in which a latch memory cell is provided for each bit line,
the CAS is activated prior to the RAS in the write cycle so that a column
address may be entered into the dRAM chip prior to a row address, while
RAS is activated prior to the CAS in the read cycle so that a row address
may be entered into the dRAM chip prior to a column address. Thus, the bit
lines are precharged during the RAS active period in the read cycle. In
the write cycle, the bit lines can be precharged immediately after the
write trigger signal WE goes from logic "0" to logic "1" to complete the
write cycle.
Moreover, the serial access can be performed by toggling the CAS in either
of the write cycle and the read cycle.
That is to say, since the bit lines can be precharged during the RAS active
period, not during the RAS precharge period as in the prior art, the cycle
time can be reduced significantly as compared to the prior art.
A third embodiment of the present invention will be described hereinafter.
The circuit arrangement of this embodiment is the same as that of the
first embodiment shown in FIGS. 1 and 2 and thus the description thereof
is considered unnecessary.
The operation in the read cycle of the third embodiment will be described
with reference to FIGS. 11A and 11B. FIGS. 11A and 11B also show signal
waveforms in performing an operation to transfer data in latch memory 20-i
onto the input/output lines in the system where the bit lines are
precharged to (1/2) VDD.
In the beginning of operation, since bit-line equalize signal EQL1 is at
the VDD level and bit-line precharging power supply VBL is at the (1/2)
VDD level, all the bit lines BL and BL have been precharged to (1/2) VDD.
Assume now that a logic "1" (VDD) is written into storage node N1 of dRAM
cell MCi1 associated with i-th bit lines BLi and BLi of interest and
storage node N3 of dummy cell DCi2 is initially set to (1/2) VDD by write
power supply VDC.
When the CAS goes from logic "1" (VIH) to logic "0" (VIL) prior to the RAS,
a column address is first entered into the chip. Where, for example, the
i-th column is selected, although column select line CSLi does not rise
from VSS to VDD at this time, the i-th column address is latched into a
decoder (not shown) for column select lines.
Subsequently, when the RAS goes from logic "1" to logic "0", equalize
signals EQL1 and EQL2 are lowered from VDD to VSS so that word line MW1 is
selected and this line and dummy word line DW2 are raised to (3/2) VDD. As
a result, the contents of dRAM cell MCi1 and dummy cell DCi2 are read out
onto bit lines BLi and BLi, respectively. In addition, equalize signal
EQL3 of latch memory cell 20-i is lowered from VDD to VSS.
The n-channel transistor activation signal .phi.SE of bit-line sense
amplifier 10-i subsequently decreases from (1/2) VDD to VSS, and then
p-channel transistor activation signal .phi.SE goes from (1/2) VDD to VSS.
As a result, bit line BLi onto which the logic "1" data of memory cell
MCi1 has been read out is raised to VDD, while bit line BLi to which the
data in dummy cell DCi2 has been read out is lowered to VSS.
Control signal .phi.T subsequently goes from VSS to VDD causing first
transfer gate 30 to be turned on. When activation signal .phi.CE goes from
(1/2) VDD to VSS and .phi.CE goes from (1/2) VDD to VDD, the contents of
bit lines BLi and BLi are transferred to nodes Ai and Ai of latch memory
20-i, respectively.
By the column address latched by the decoder for column select lines,
column select line CSLi is raised from VSS to VDD so that nodes Ai and Ai
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