This circuit is a trunk type interface circuit which interfaces between duplicate copies of an ISDN system and T-carrier facilities. The circuit is controlled by a digital signal processor which has a 16-bit wide data bus. The digital signal processor is capable of supporting various Zero Byte Time Slot Interchange (ZBTSI) techniques. Also included is an administrative microprocessor which collects data concerning the operation of the trunk circuit and transmits this information to the ISDN system. The administrative microprocessor also receives information from currently unused data bits in the input bit stream from the ISDN system. The trunk circuit includes one receiver which collects and stores data transmitted by the ISDN system. Another receiver collects and stores data transmitted via the T-carrier facilities. The trunk circuit also includes two transmitters. One transmitter converts previously formatted data to T-carrier compatible data and transmits the data via the T-carrier facilities. the other transmitter converts reformatted data received from the T-carrier facility to data compatible with the ISDN format and transmit this data to the ISDN system. The memory of this circuit includes a dual port random access memory which provides for nearly simultaneous access by two separate input/output controllers.
A serial optical link for transmission of payload data is utilised so as to permit transmission of information facility data unrelated to the payload data. A superframe is constructed at the transmission facility made up of a serial series of data frames. Each data frame consists of serially arranged words including a number of payload data words and a non-payload word. One non-payload word of the superframe has information facility data which provides a communication channel from the transmitting facility to the receiving facility for information unrelated to the communication of payload data. Another non-payload word has alarm and status facility data. The information facility data is stored in a FIFO buffer when received. If the FIFO buffer is within two words of being full, a full signal is incorporated in the next alarm and status facility data word which causes the receiving end to suspend sending information facility data words.
A serial port having a pattern generation mode and a microprocessor using same. The serial port uses a transmit circuit controlled by a state machine which determines whether start and stop bits are transmitted by a computer implemented method. In pattern generation mode, start and stop bits are not transmitted, and the serial port lends itself to transmitting pulse width modulation data. In one embodiment, the serial port is used in a microprocessor which includes a central processing unit (CPU) and a bus interface unit.
