A register device includes a register set group, a switching control unit, a write control unit, a write flag memory unit, and a read control unit. The register set group consists of a plurality of register sets each constituted by a plurality of registers. The switching control unit selects a register set to be used in processing from the register set group in response to a saving/recovery instruction. The write control unit writes data in registers of the register set selected by the switching control unit in response to a write instruction. A write flag representing whether data is written in each of the registers is held by the write flag memory unit. The read control unit determines, in response to a read instruction, a register in which data is written most recently of a plurality of registers corresponding to each other between the register sets with reference to the write flags, thereby reading out data from the register.
An integer processing unit for a reduced instruction set computer having a plurality of registers arranged in groups referred to as register windows, each window register group including a number of input registers, a similar number of output registers, and a number of local registers, the register window groups being physically arranged so the input registers of each group are the same physical register as the output registers of the next adjacent register window group thereby forming one large interconnected ring of register window groups, an arrangement for designating the register window group presently active, and an arrangement for designating register window groups which are not available for use.
According to this invention, a computer includes a register use information detecting unit for extracting pieces of information of registers, use of which is started and ended by executing instructions of a program, a register use information storing unit for storing information of a register whose value need be stored to execute an instruction in the program, a register use information referring unit for referring to register use information of the register use information storing unit, an instruction executing unit for executing predetermined processing for a desired register in accordance with a reference result of the register use information referring unit, and a register use information updating means for updating use information of a register stored in the register use information storing unit in accordance with outputs from the register use information detecting unit and the instruction executing unit.
A circuit configuration includes at least one nonvolatile, electrically erasable and writable memory area. Each memory area is assigned a nonvolatile, electrically writable and erasable flag memory, which is connected through an address line, a programming line and an authentication line to the assigned memory area, a programming voltage source and a data verification circuit. In the event of an alteration in the content of a memory area, the state of the associated flag memory is changed and, after verification of the programmed memory area content, the flag memory is returned to its basic state.
A microprocessor 1 is coupled to a memory 2, and includes an instruction pipeline 3 and a register file 4. The register file 4 includes an address read/write circuit 5, a plurality of frame address storing registers 6 coupled to the address read/write circuit 5, data read/write circuits 7 and 10, and register banks 8 of the same number as that of the frame address storing registers 6. The register banks 8 is coupled to the data read/write circuits 7 and 10, and all the register banks 8 are composed of the same number of registers 9. The instruction pipeline 3 is coupled to the register file 4 through a register designating bus 104, a data transfer bus 105, and an address transfer bus 106. The instruction pipeline 3 is also coupled to the memory 2 through a memory address bus 101 and an instruction supply bus 102, and the data read/write circuit 10 is coupled to the memory 2 through a data transfer bus 103. At the time of the context switching, the overhead required for the save/restore of the content stored in the register file can be reduced.
The assembly comprises a circuit for detecting errors in data supplied by at least one of the blocks of the assembly. When an error has been detected, the assembly is decontaminated by one circuit for backup and reconstitution of past states of a latch associated to a block. The backup and reconstitution circuit comprises a multiplexer and buffer register. The multiplexer comprises a first input directly connected to the output of the latch and a second input connected to this output via the buffer register. A control circuit controls the buffer register and the multiplexer so as to activate the buffer register writing function and connect the output of the multiplexer to its first input at each cycle, during a normal operation phase, and to read enable the buffer register and connect the multiplexer output to its second input during predetermined cycles of a decontamination phase.
