In methods and apparatus for testing a digital system, system terminals used for coupling input signals into the system and output signals out of the system during normal operation of the system are connected in parallel to a single boundary register. The boundary register is operable to pass input signals and output signals transparently through the boundary register while accumulating together the input signals and the output signals. For testing purposes, the digital system and boundary register are run through a predetermined number of clock cycles while passing known input signals through the boundary register into the system. The known input signals and output signals provided by the digital system are concurrently accumulated within the boundary register to generate a test result pattern. In an alternative method and apparatus the boundary register is operable to generate input signals and to pass said input signals from the boundary register to selected system terminals while receiving output signals from selected system terminals and accumulating together the input signals and the output signals. The methods and apparatus are particularly useful for testing digital integrated circuits and systems comprising digital integrated circuits in their normal operating configuration and at their normal operating clock rates.
An electronic system includes electronic circuitry to be tested having serial scan shift register latches, and a serial scan generator embedded in the electronic system upon manufacture and connected to the serial scan shift register latches of the electronic circuitry to facilitate testing. The electronic system may consist of a single printed circuit board mounting both the electronic circuitry and the serial scan generator. The electronic system may consist of a single semiconductor chip carrier mounting both the electronic circuitry and the serial scan generator, are both mounted on said single semiconductor chip carrier. The electronic system may further include a detachable second serial scan generator. The serial scan generator preferably operates slower than the detachable second serial scan generator. The electronic system may further include a disabling terminal disabling the serial scan generator upon attachment of the detachable second serial scan generator.
A testing device comprises a plurality of pin test portions, each of which is separately provided with a pin pattern controller for controlling the readout of pattern and timing data from pattern and timing memories and a pin instruction memory for storing programs defining the operation procedure of the pin pattern controller. Therefore, the data to be stored in the pattern and timing memories in each of the pin test portions can be in a compressed form, independently of the data to be stored in the pattern and timing memories in the other pin test portions.
A highly-integrated semiconductor IC device includes a semiconductive substrate, on which an internal function circuit is arranged to have a first plurality of input terminals and a second plurality of output terminals. A logic circuit is arranged on the substrate and is connected to the internal circuit through the output terminals. The logic circuit has a third plurality of output terminals, which are less in number than the outputs of the internal circuit. These logic output terminals are coupled to the same number of inspection terminals, which are adapted to be coupled to a known electric inspection tool. The logic circuit processes the voltage signals appearing at the output terminals of the internal circuit so as to cause these signals to decrease in number. The output signals of the logic circuit are sent to the inspection terminals as monitor signals, based on which an inspection is carried out to determine whether the internal circuit operates normally.
A test access port controller for use in a level sensitive scan design having test design logic including at least one serial scan test path. The test access port controller includes test access port controller logic operable in a system test mode for controlling the serial shifting of input test data into the at least one serial scan test path and for controlling serial shifting of resulting output test data out of the at least one serial scan test path after performance of system mode test under control of a test clock. The test access port controller further includes clock logic for providing the test clock to the test access port controller logic and the test design logic in system test mode. The clock logic further provides a system clock to the test access port controller logic and test design logic in a fabrication test mode to serially shift input test data into the test access port controller logic and test design logic and to serially shift resulting output data out of the test access port controller logic and test design logic after operation of the test access port controller logic and test design logic under one cycle of test clock. A test method for such level sensitive scan designs includes serially shifting input test data into the test access port controller and the test design logic under control of the system clock. Then the test access port controller is operated under control of the test clock for at least one cycle to generate resulting output test data. The resulting output test data is serially shifted out of the test access port controller and the test design logic under control of the system clock.
An integrated circuit is described having a scan chain of the JTAG type in which there are provided a plurality of serially connected test cells 2. The test cells serve the additional function of operating during the normal operation of the integrated circuit to store signal values that are logically combined (compared) with signal values generated by the integrated circuit to yield control signals into for controlling the operation of the integrated circuit. This allows the storage capacity of the test cells to be utilised during normal operation when they would otherwise be idle.
