The present invention teaches a new method for formation of thin dielectrics over polysilicon. This technique permits the fabrication of poly-to-poly capacitors with high specific capacitance (capacitance per unit area). This technique is completely compatible with standard MOS dual poly regrown gate oxide processes. The high value of specific capacitance is achieved by using a composite dielectric which has high dielectric integrity and whose thickness is completely independent of the formation of the regular gate oxide under the second poly. No extra mask steps are required. The composite dielectric is formed as a grown or deposited oxide followed by a deposited nitride which is then reoxidized. Optionally, a second oxide is deposited before reoxidation performed.
This application is a continuation of application said Ser. No. 07/113,402 filed Oct. 23, 1987, abandoned, which is a continuation of application Ser. No. 06/846,829, filed Mar. 31, 1986, abandoned, which is a continuation of application Ser. No. 06/756,637, filed July 19, 1985, abandoned, which is a division of application Ser. No. 06/468,920, filed Feb. 23, 1983, U.S. Pat. No. 4,577,390.
An electric device comprises a crystalline film deposited on a substrate and an electrode formed on the film. The crystalline film consists of a number of colomnar crystal grown at right angles from the surface of the substrate. There are many grain boundaries passing through the crystalline film from the substrate surface to the electrode. The direct contact between the electrode and the grain boundaries is prevented by means of an insulating coating applied only to the portion of surfaces of the columnar crystals where the boundaries appear.
A semiconductor integrated circuit device includes a capacitor and a resistor in addition to a transistor. The capacitor includes a lower electrode made of a first polysilicon layer formed on an insulating layer covering the main surface of a semiconductor substrate, a dielectric film formed on the lower electrode and a upper electrode formed on the dielectric layer, whereas the resistor includes a resistor layer made of a second polysilicon layer formed on the insulating film. The first polysilicon layer has the same sheet resistance as the second polysilicon layer.
A semiconductor structure having a high precision analog polysilicon capacitor with a self-aligned extrinsic base region of a bipolar transistor is disclosed. The structure is formed by simultaneously forming the dielectric layer of the capacitor with the formation of the base region of the bipolar transistor. A final oxidation step in the formation of the capacitor causes the base region to diffuse to form a self-aligned extrinsic base diffusion region.
The present invention teaches a method for fabricating an ultrathin uniform dielectric layer over a silicon or polysilicon semiconductor substrate. The method entails first providing a substrate having a conductive area into a chamber. Subsequently, the first conductive material is destabilized by introducing it to reactive gas and radiant energy in situ. The reactive gas can be Ar-H.sub.2, H.sub.2, GeH.sub.4 or NF.sub.3 gas. The radiant energy source can be ultraviolet ("UV") or Tungsten Halogen lamps preferably having an approximate range of 0.2 to 1.6 .mu.m to provide heat of approximately 850.degree. to 1150.degree. C. for approximately 10 to 60 seconds at a vacuum pressure range of 10.sup.-10 Torr to atmospheric pressure. This process removes the native oxide and breaks the molecular clusters present on the silicon or polysilicon surface. Thereafter, a first dielectric layer having a substantially uniform thickness forms directly above the substrate by the in situ introduction of NH.sub.3 with the radiant energy generating heat of approximately 850.degree. to 1150.degree. C. for approximately 10 to 60 seconds at a vacuum pressure range of 10.sup.-10 Torr to atmospheric pressure. Finally, a second silicon nitride layer is deposited by low pressure chemical vapor deposition or plasma nitridation to create a combined thickness of both dielectric layers of 40 to 100 .ANG..
Disclosed is a semiconductor device having low voltage characteristic and advantageous integrity simultaneously. The semiconductor device comprises a silicon-on-insulator (SOI) substrate of a stack structure comprising a base layer as a means for supporting, a buried oxide layer, and a semiconductor layer providing an active region; and a first transistor and a second transistor formed on the active region of the SOI substrate, wherein the first and second transistors are formed as a stack structure on one active region and they share one gate electrode, a drain region of the second transistor is electrically connected to the gate electrode and a source region of the second transistor is electrically connected to the active region.
