A method to adjust the divisor and dividend, for application to a divider, so that the mantissa part of the divisor is transformed to be within a known limited range. The limiting of the transformed divisor range enables the complexity of the quotient select logic to be reduced accordingly. Once the divisor is restricted to the selected range, the dividend is adjusted proportionally so the quotient is unchanged.
A special carry save adder includes structure for performing multiple addition operations, common input structure to the structure for performing multiple addition operations, and mixing structure for selecting the desired result of the multiple addition operations.
A higher-radix type divider is provided which is capable of obtaining a quotient at a high speed by performing a scaling on a divisor and by representing a partial remainder in a redundant binary notation. The divider for obtaining the quotient by referring to the divisor and dividend normalized respectively so as to satisfy a range of 1/2.sup.K or more and less an 1/2.sup.K+1 (k being a positive integer) and to a length of bits, out of all bits of the partial remainder, defined by a radix for operations and a maximum number of digits, is provided with a scaling factor generating section, a multiplying section, a divisor tripled-number generating section and a repetitive operating section.
For dividing a dividend of a first plurality of m-ary digits by a divisor of a second plurality of m-ary digits to provide a certain number K of m-ary quotient digits, where m represents 2.sup.N, a shift register comprises a most significant part, first and second higher parts for the second plurality less one of m-ary digits and one m-ary digit, and a least significant stage and holds an instantaneous content which is used as a current content during a last part of a preceding one of two consecutive machine cycles and is first a concatenation of an m-ary zero digit and the dividend m-ary digits. A carry save adder tree calculates a set of zeroth to (m-1)-th algebraic sums of a part of the current content held in the most significant and the first and the second higher parts minus zero through (m-1) times the divisor, respectively, plus a carry from a previous machine cycle. The sums are used in deciding a partial quotient of one m-ary digit and a sum datum of the second plurality of m-ary digits. In a leading part of a succeeding one of the consecutive machine cycles, the partial quotient and the sum datum are stored in the least significant stage and the most significant and the first higher parts. After lapse of K machine cycles, the shift register is loaded with an eventual quotient in its stages other than the most significant and the first and the second higher parts.
An apparatus for performing floating-point division and square root computations according to an IEEE rounding standard includes input data alignment circuitry, core iteration circuitry, remainder compare circuitry, and round and select circuitry. The core iteration circuitry includes digit selector circuitry; remainder registers; quotient logic circuitry; remainder formation circuitry; and quotient registers for storing the quotient Q, incremented quotient Q+1, and decremented quotient Q-1. The remainder formation circuitry produces sum and carry bits of the P.sub.j+1 term, which are in turn fed back to the partial remainder registers and used in subsequent iterations. The quotient logic circuitry builds the quotient Q and maintains the respective quotient Q, Q+1, Q-1 registers. The outputs of these registers are fed back to the quotient logic circuitry for use in subsequent iterations. The remainder compare circuitry comprises a remainder comparator and a logic circuit. The remainder comparator receives the sum and carry bits for the P.sub.j+1 terms and outputs the "Sign" and "Zero" bits. These bits are received by the logic circuit along with a rounding mode signal, which is indicative of the selected rounding mode, e.g., shifted or normalized round to nearest, round to zero, or round to infinity. The logic circuit outputs a round select signal that selects a quotient select signal for selecting, as the final rounded quotient, the output of one of the quotient registers Q, Q+1, or Q-1. The round and select circuitry includes a round block for positive remainders and a round block for negative remainders.
A hardware logic arrangement for quotient correction in high speed higher radix non-restoring division computation circuits producing alternative quotient results of the form Q and Q-1. A two bit per clock quotient bit stream is taken as the output from an divider and selectively latched into positive and negative weighted quotients. These redundant vectors are then seperately steered via appropriate steering logic to a carry-propogate-adder (CPA). An exclusive-OR (XOR) logic block is inserted between the steering logic for one of the vectors and the subtrahend input of the CPA. Operation of the XOR block is governed by a first control signal. A second control signal is coupled to the carry-in input of the CPA. After the last iteration of the division sequence, either Q or Q-1 alternative forms of the result quotient may be produced in the clock cycle required by selectively invoking 2's complement addition when combining the redundant weighted quotients. Where the quotient Q is required, asserting the first control signal to the XOR block inverts the datavalue transmitted to the subtrahend input of the CPA, whereafter both addend and subtrahend inputs are added together in the presence of the second control signal asserted to the carry-in input of the CPA, adding 1 to the sum. Where the alternative result Q-1 is required, only the first control signal is asserted to the XOR block to invert the datavalue transmitted to the subtrahend input of the CPA, whereafter the addend and subtrahend inputs are simply added together.
