There is disclosed a video processor capable of arbitrarily expanding or contracting an image in a vertical direction. A horizontal synchronizing signal HS of a video signal CS is inputted to a reference input terminal 63a of a phase comparator 63 of a PLL circuit 62 to take out a clock signal CK having a frequency N1 times larger than that of the horizontal synchronizing signal HS. This clock signal is frequency-divided by N2. Since N2 is set to the number of horizontal synchronizing signals within a vertical synchronous period, the number of sampling lines in a vertical direction becomes equal to N1. Accordingly, when an output signal (line clock signal LCK) of the frequency divider 67 is used as a signal for increment of a vertical address of a video memory 70, enlargement/contraction of an image can be carried out by changing N1.

Disclosed is an address producing circuit for zoom function in which horizontal and vertical addresses are to make more free selection of a partial picture around a plurality of locations disposed on a screen of a monitor device, and image data stored in a predetermined address region according to the selection is read out to display on the screen, so that the picture of the selected partial region can be magnified to a whole screen picture.

An expanded-image generating apparatus is provided for original image data, in which a plurality of pixels is arranged in a matrix, so as to obtain expanded-image data partitioned into a plurality of blocks, each of which is composed of a plurality of pixels When the magnifying power regarding at least one of a direction along width and a direction along length in the original image data is set, a pixel arranging processor arranges each pixel in the original image data at a position corresponding to a center position of each of the plurality of blocks in accordance with the magnifying power. The expanded-image data corresponding to the magnifying power is generated at pixel generating positions corresponding to the each block by applying a fluency transform to each pixel in the original image data at the position. When the magnifying power is odd numbered, a shifting processor shifts said pixel generating positions relative to each corresponding pixel of said original image data by a shifting-amount corresponding to said magnifying power such that each arranged pixel of said original image data is off-center with respect to said plurality of blocks.

A video processor which is capable of arbitrarily expanding or contracting an image in a vertical direction is described. A horizontal synchronizing signal HS of a video signal CS is inputted to a reference input terminal 63a of a phase comparator 63 of a PLL circuit 62 to take out a clock signal CK having a frequency N1 times larger than that of the horizontal synchronizing signal HS. This clock signal is frequency-divided by N2. Since N2 is set to the number of horizontal synchronizing signals within a vertical synchronous period, the number of sampling lines in a vertical direction becomes equal to N1. Accordingly, When an output signal (line clock signal LCK) of the frequency divider 67 is used as a signal for increment of a vertical address of a video memory 70, enlargement/contraction of an image can be carried out by changing N1.

A display control circuit that enables efficient image rotation, and scaling of bit-mapped image data stored in image memory, in synchronization with dot clock, line, or frame timing of a target display device without requiring re-writing of the display memory contents. Addresses output from a memory address counter are modified by multiplication and summation with desired image display parameters to generate new addresses for retrieving desired image data from memory locations that are physically mapped to the modifications desired for a new output image. The basic image data is not itself modified. Timing of multiplication and summation processes is synchronized to the timing of the target display device and is performed during horizontal or vertical retrace line intervals. Additional summations of address values with the display parameters is performed by dot and line. It is, therefore, possible to achieve smooth image rotation without relying on high clock rate multiplication operations timed to the dot clock frequency by using a multiplication operation once every display frame or line, and a cumulative addition operation once every dot or display line. Multipliers can operate at a low clock rate, and time-shared use is possible, enabling the circuit to be constructed on a small scale and at low cost.