A mask layer is formed on a conductive layer covering not only a central area assigned to integrated circuits but also a vacant peripheral area of a semiconductor wafer, and an electroplating system allows metallic miniature patterns to grow on the conductive layer over the vacant peripheral area as well as extremely small areas of the conductive layer over the central area so as to make current fluctuation negligible.

A method for manufacturing a semiconductor device of the present invention comprises the following steps (1) through (7) of, (1) forming a lower insulation film thicker than a metal wiring layer to be formed in order on a semiconductor substrate, a first conductive film and an upper insulation film; (2) removing the upper insulation film in the wiring formation area and then exposing the lower insulation film by etching the first conductive film; (3) forming concave grooves in the lower insulation film by etching the film using as a mask the upper insulation film whose wiring formation area is removed or a photoresist applied to the patterning of the upper insulation film; (4) forming a second conductive film on the whole surface including the concave grooves and successively forming sidewalls made of the insulation film in the sides of the grooves; (5) forming metallic wiring layers by electrolytic plating in the grooves wherein the said sidewalls have been formed by electric power supplied from the second conductive film; (6) removing the sidewall, the second conductive film and the upper insulation film all in the area where no metallic wiring layer exists, and (7) removing the first conductive film.

A circuit board comprising a base having a substantially flat surface and an insulative layer made of a heat-resisting synthetic resin formed on the flat surface of the base. The insulative layer is provided with grooves for forming conductive parts, and each of the groove is defined by a bottom surface formed by the base and side walls formed by the insulative layer. A conductive adhesive layer having a good adhesion characteristic with respect to the base, such as Cr, is formed on the bottom surface of the grooves, and a conductive layer is formed on the conductive adhesive layer so that a surface defined by the insulative layer and the conductive parts including the conductive layer and conductive adhesive layer is substantially flat.

A method of manufacturing a wiring board, including: providing a resin substrate on which is formed a metal layer including a first layer and a second layer formed on the first layer; forming an interconnecting pattern by etching the metal layer so that the interconnecting pattern includes the patterned first layer and second layer and a part of the first layer remains outside the second layer as a residue of the first layer; electroless plating the interconnecting pattern and the residue of the first layer; and then washing the resin substrate. The washing of the resin substrate is performed by using at least one of an acidic solution used for dissolving and removing the residue of the first layer and a metal deposited on the residue of the first layer by the electroless plating and an alkaline solution used for dissolving the resin substrate to remove an area which supports the residue of the first layer.

Poor sidewall coverage of vias in substrates for multi-chip modules is alleviated by forming pillars associated with conductors on an underlying metal wiring layer. In one embodiment, the pillars are disposed underneath the conductors, causing portions of the conductors to be pushed up through an overlying insulating layer towards a metal layer overlying the insulating layer. The pillars can be electrically conductive or insulating, and can be thermally conductive. In another embodiment, the pillars are disposed atop the conductors, thereby extending at least partially through the insulating layer. These pillars are electrically conductive.