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Description  |
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BACKGROUND AND SUMMARY
1. Technical Field
The present invention relates generally to the field of audio recording and
playback systems. More particularly, it relates to the field of digital
audio recording and playback systems.
2. Background Art
Typical audio recording systems known in the art use magnetic tape, drums
or disks as storage media for storing audio signals for later playback. An
audio sensor or detects analog audio signals which are converted to
electronic pulses. The storage medium typically is mechanically rotated to
expose an unwritten section thereof to an electronic unit which records
the incoming signal on the medium.
Such systems suffer from various disadvantages. For example, the mechanical
parts of the system may wear, especially those parts which rotate or
otherwise move. The media themselves may be damaged in normal use, as when
a tape is stretched or a disk is scratched, thereby decreasing the quality
of the recording and playback. Moreover, the mechanical parts of those
systems usually require periodic maintenance or replacement. Such systems
also suffer from a limitation on the ability of the user to select
randomly a portion of the recording to be played. That is, the messages
must be accessed serially, as, for example, by rewinding the recording
tape. And the portion of the recording desired may be difficult to locate
readily, resulting in excessive search and effort.
3. Summary of the Invention
The present invention is an improvement of the digital recorder/player of
U.S. Pat. No. 4,772,873 to the present inventor, which is incorporated
herein by reference. The present invention is a modular system for digital
random access recording and playback of audio signals. A single module may
comprise one logic board, and up to sixteen channels. Each of the channels
may have up to sixteen memory boards per channel. A power supply and
interconnect cables also are provided. An entire system may comprise
several modules. In a system with four modules, for example, there could
be four independent audio sources, a crystal controlled master oscillator
to provide uniform clocking to the modules, four logic boards, up to 1,024
memory boards, a power supply and interconnect cables. A timer may also be
provided for timed random access recording and playback.
Preferably, according to the present invention, an audio signal is picked
up and filtered by an analog filter which blocks DC and very low
frequencies. Then the signal is filtered by digital filters to prevent
foldover distortion of the analog audio signal. One of the digital filters
also preferably generates a clock, although it can be slaved to an
external clock. The other filters and an analog to digital/digital to
analog converter (ADC/DAC) are slaved to the digital filter clock to
prevent harmonic heterodyning. A master oscillator may be provided in a
system incorporating multiple modules.
Preferably, the ADC/DAC is a continuous variable slope delta (CVSD)
modulator system which samples the analog audio signal at a uniform
frequency. The digital signal output of the ADC is fed to a memory board.
The clocking for the CVSD and for the logic board is derived, through a
divide-by-eight counter, from the digital filter clock. The logic board
controls one module of the system and serves as the controller for the
memory boards, an encoder for analog to digital conversion, a decoder for
digital to analog conversion, an interface for the system and module
controls, and provides clocking for each individual module.
The memory of each module of the system of the present invention preferably
includes up to sixteen channels, each having up to sixteen memory boards.
The memory technology may include CMOS static RAMs, EPROMs or EEPROMs. To
accomplish random accessing, each of the channels is addressed by a unique
four bit binary code and each of the memory boards is addressed by a
unique four bit binary code. Thus, a complete address for a particular
memory board of a particular channel is an eight bit code including the
unique channel code and the unique board code. Each board of a particular
channel will have the same four bits of channel code and a different four
bit board code.
The logic board communicates with the memory of the system via a memory
buss which includes a 34 line edge pin connector which connects with all
memory boards of the module. The logic board includes a "D" flip-flop to
define the reset and play modes. When power is first applied to the logic
board, the logic board resets. Random access for the recording and play
modes is achieved by each memory board using two four bit comparators, one
which compares the four bit channel code on the memory buss with the
setting of a four bit switch, and one which compares the four bit board
code on the buss with the four bit switch on the memory board itself. An
external control switch selects the record or play mode and selects a
channel and memory board to receive recorded data or from which data are
played back. When there is a match of codes, the memory control logic on
an individual memory board is enabled and data is written to or retrieved
from a particular memory board.
The logic board is also provided with channel and memory board counters for
the sequential use of the channels and memory boards in a module. That is,
the first memory board of the first channel is filled with messages first,
then the second memory board of the first channel, and so on through the
sixteenth memory board of the first channel. Then the second channel is
enabled, and each of its memory boards is filled sequentially. The process
continues until all 256 memory boards of the sixteen channels are filled.
Alternatively, the present invention provides for external control of the
channel and memory board selection to provide random access to the memory.
During the record cycle, a selected memory chip is enabled to read incoming
data, and data are passed in serial format from the logic board to the
selected memory board to be converted to parallel format by a serial to
parallel converter, and data are strobed into memory.
During the playback cycle, the control logic on the memory board selects a
memory chip, the data corresponding to an address supplied by address
counters. The data are converted from parallel to serial format by a
converter and are transmitted back to the logic board for conversion from
digital to analog signals. The analog signal is filtered and amplified
before passing to an audio signal output device such as a loudspeaker.
By providing for digitalization of an audio signal and storage of the
signal in digital form in a memory and by providing for random access of
the signals so stored, the present invention overcomes disadvantages and
limitations of audio recording systems of the past.
Accordingly, it is a primary object of the present invention to provide an
audio recording and playback system which converts an audio signal to
digital form and stores the digital signal in a memory such that random
access for recording and playback is achieved.
It is another object of the present invention to provide a digital audio
recording and playback system with a memory unit having a plurality of
channels, each channel having a plurality of memory boards, and in which
channels and memory boards can be randomly accessed.
These and other objects, features and advantages of the present invention
are described in or are apparent from the following detailed description
of a preferred embodiment.
BRIEF DESCRIPTION OF THE DRAWINGS
The preferred embodiment will be described with reference to the drawings,
in which:
FIG. 1 is a block diagram generally showing the relationships of the main
components of one module of a digital audio recording and playback system
constructed in accordance with the present invention.
FIG. 2 is a block diagram showing a system according to the present
invention having a plurality of the modules shown in FIG. 1.
FIG. 3 is a timing diagram for the clocking system of the present
invention.
FIG. 4 is a schematic diagram of part of the memory unit of the present
invention.
FIG. 5 is a schematic diagram of part of the memory unit of the present
invention.
FIG. 6 is a schematic diagram showing the relationships of a variable
length message control to the logic board of the present invention.
FIG. 7 is a schematic diagram of part of the logic board of the present
invention.
FIG. 8 is a schematic diagram of a part of the logic board of the present
invention.
FIG. 9 is a schematic diagram of part of the logic board of the present
invention.
FIG. 10 is a diagram showing the external control unit for the memory
boards of the present invention.
FIG. 11 is a schematic diagram showing the external control circuit of the
present invention.
FIG. 12 is a schematic diagram of the variable length control of the
present invention.
FIG. 13 is a schematic diagram of part of the audio output circuit of the
present invention.
FIG. 14 is a schematic diagram of part of the audio output circuit of the
present invention.
FIG. 15 is a schematic diagram of part of the audio output circuit of the
present invention.
FIG. 16 is a schematic diagram of the master oscillator of the present
invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
Referring to FIG. 1, a block diagram of the relationships of the main
components of a preferred embodiment of one module 11 of a multi-channel
digital random access recorder-player 10 of the present invention is
shown. The particular subcomponents of each main component shown in FIG. 1
will be discussed in more detail below. Generally, FIG. 1 shows a signal
processor, including an analog filter 14, a digital filter 16, an ADC/DAC
20, a counter 18 and a clock 17, coupled to a module which includes a
logic board 22, an external control 24, a memory buss 28, and a memory
board 26. Memory board 26 includes channel code comparator 25, board code
comparator 27, serial-to-parallel/ parallel-to-serial converter 29, memory
storage chips 32, memory manager 30 and back-up battery 31.
An analog signal input 12 is filtered by an analog filter system 14 for
blocking DC and very low frequencies and by a digital filter 16. Circuit
16 digitally filters the input signal to prevent foldover distortion of
the analog signal during sampling. A clock 17 generates a clock signal
which is used by the entire system. As shown, the single clock signal from
clock circuit 17 is a part of digital filter 16, and is divided by counter
18 to provide the correct timing for the other components of the system,
as described more fully below.
The output signal from digital filter 16 is converted from analog to
digital by analog-to-digital/digital-to-analog converter (ADC/DAC) 20,
which preferably is a continuous variable slope delta (CVSD) modulator
system, the sampling rate of which is set by the output of counter 18.
The output of ADC/DAC 20 is fed from logic board 22 which serves as the
controller for a memory unit 26 and as an interface with an external
control 24, as well as the rest of the system. The clocking for memory
board 26 also is provided by digital filter and clock circuit 17 via
counter 18. Logic board 22 communicates with memory unit 26 via a memory
buss 28 which includes a 34 line edge pin connector.
Memory unit 26 may include up to sixteen channels, each of the channels
having up to sixteen memory boards 26. FIG. 1 shows only two
representative channels and one representative memory board 26 for each
channel. Each memory board 26 is assigned a unique address and data from
logic board 22 may be recorded in memory by sequential filling of each
memory board of each channel, if desired. That is, a first memory board 26
of a first channel is filled with data, then the second memory board 26 of
the first channel is filled with data, and so on until all memory boards
of the first channel are filled. Then, data are entered in the first
memory board 26 of the second channel, and so on in sequence. Data may be
retrieved in the same sequential manner if desired.
Each module 11 of recorder-player 10 provides random access, both for
recording and playback modes when sequential recording and playback is not
desired. In random access recording, the record mode is selected by the
user or by an external control 24, and the correct four bit board and
channel codes are strobed in through external control 24 to preset the
channel address counter and memory board address counter to the desired
channel and board number. The selected addresses are placed on memory buss
28 and are fed into two comparators 25 and 27 on memory board 26.
Comparator 25 compares the four bit channel address present on memory buss
28 with the channel addresses set by four bit switch 21 on memory board 26
and comparator 27 compares the four bit board address present on memory 28
with the four bit switch 33 on memory board 26. When the addresses present
on memory buss 28 match the addresses on memory board 26, then the board
and channel comparators 25, 27 enable the memory management unit 30 and
the address counter 34. Data from logic board 22 may then be written to
the memory board 26 with the matching board and address code.
In a similar manner, random access playback is achieved by the digital
recorder-player 10 of the present invention. The user, by manual or
automatic selection, sets a mode switch on external control 24 to playback
position and strobes the correct address through the computer port 23 to
the external control 24 to select the desired channel and board number.
The address selection at external control 24 is compared by comparators 25
and 27 with the addresses of the channel and board address counters 19 and
15 on the logic unit 22. When a match between the addresses is found,
comparators 25 and 27 enable the selected memory board 26 to read and
place data in a serial format on memory buss 28 to logic board 22.
An analog audio input signal 12 is converted to digital by ADC/DAC 20 in
the record mode. In playback mode, the digital data bits from memory unit
26 are converted back to the original audio program by ADC/DAC 20.
As noted above, the many types of A to D and D to A converters or
processes, the present invention preferably includes the continuous -
variable - slope - delta modulator system, called CVSD. This system design
relies on the delta modulation technique.
In a CVSD modulator, a reference waveform, resulting from integrating three
output bits, is subtracted from the sampled input waveform. Each output is
one bit per sample. If the difference is a positive quantity, the output
bit of the next sample will be a "1"; if the difference is negative, the
output bit of the next sample will be a "0". This reference waveform,
therefore, moves positively or negatively by one increment or by one step
with each sample. The reference waveform is set to zero by initializing
the integrators to zero before each message is played or recorded.
This technique can reduce or even reverse the polarity of the difference
between two steps or samples. The modulator now becomes a negative
feedback system with output bits which allow the reference waveform to
follow the input signal. Delta modulation is a special case of
differential PCM (Pulse Code Modulation), with only one bit per sample and
the output bit rate equal to the sampling frequency. CVSD is a particular
type of adaptive delta-modulation.
CVSD requires no precision components and can be manufactured economically.
As all bits have equal weight, isolated bit errors have a very minor
audible effect. When combined with the commanding properties of CVSD,
differential coding more closely matches the properties of human hearing.
In the CVSD system, overloads of short duration have a minor audible effect
and/or may even be undetectable. The CVSD system can recover from dynamic
audio overload in one to three cycles. However, there is no absolute audio
signal value, but only the change in signal value from sample to sample.
To overcome this problem, the CVSD system of the present invention always
starts recording at zero value and all playbacks start at zero value. This
provides excellent agreement with absolute audio signal value.
Due to the dynamics of CVSD digital audio recording, conventional sine wave
testing is not necessarily a true indication of the audio quality. A form
of dynamic testing should be employed.
In performing the A to D conversion, samples of the analog audio signal 12
are taken at a uniform frequency. Thus, sampled data systems require the
output signal to be band limited. This applies to audio. This sampling has
been defined by the Nyquist Theorem, Shannon and others. The Nyquist
theorem derivation assumes a sinusoidal input and employs trigonometric
identities to reach a conclusion. For dynamic audio signals, the sampling
frequency must be higher than the Nyquist frequency to obtain a
representative signal.
To control the bandwidth and perform band limiting, digital filters are
used. In the past, fixed passive devices or fixed active filters were
used. If changes were made in the sampling frequency or in the bandwidth,
it was necessary to do a complete new design and to change the components.
With digital filters, the only change required is the clocking frequency.
See U.S. Pat. No. 4,772,873.
Clocking for the digital logic board 22 and ADC/DAC 20 advantageously is
derived from the clocking frequency of clock 17. This prevents heterodyne
and beat frequency interference as all of the clock frequencies are
synchronized. Where fixed clock frequency is required, the clock is
determined by an RC time constant or a crystal as part of clock 17.
However, external clocks may be used. For a variable frequency clock, the
resistor is replaced with a trimpot and the capacitor is held constant.
This combination of clocking and digital filtering provides any number of
audio bandwidth/playtime characteristics. Only one control is required.
This digital clocking technique is covered under U.S. Pat. No. 4,772,873.
The multi-channel recorder-player of the present invention is a modular
concept. A minimum configuration can be made up with one logic board 22
and one memory board 26 (with 2 megabits or 2,048 kilobits of memory) plus
power supply and interconnect cable. A module can be made up with one
logic board 22, and up to 16 channels. Each channel may contain up to 16
memory boards 26 per channel. A complete module would include a logic
board 22, a total of 256 memory boards 26 (over 512 megabits or 524,288
kilobits of memory), plus power supply and interconnect cable. Audio
bandwidth is controlled by only one simple adjustment from 2.5 kHZ to 10
kHZ. Record/play time per memory board 26 is from 2 minutes 11 seconds at
2.5 kHZ to 33 seconds at 10 kHZ. Therefore, a module will have a
record/play time from 9 hours 19 minutes at 2.5 kHZ to 2 hours, 11 minutes
at 10 kHZ and a 4 module system will be from 37 hours, 18 minutes at 2.5
kHZ to 9 hours, 19 minutes at 10 kHZ.
With reference to FIG. 2, the digital random access recorder-player 10 of
the present invention can include four modules. This provides 4
independent audio sources 37, plus crystal control master oscillator 39,
power and interconnect cables. A system could have 4 logic boards and
1,024 memory boards (over 2,147 megabits of memory). Each channel 35 and
each memory board 26 in a channel 35 may be addressed in any random manner
by an external input from a CPU, manual controller or timer represented in
FIG. 1 through external control 24. Control of a single module is possible
through a 16-position hex switch, and a start sequence push button
represented by manual control board 36 through the computer port
represented in FIG. 1 as 23.
Messages may be loaded by direct audio input (-5 dBm, 600 Ohm, unbalanced)
or by external digital input, local or remote. Power requirement is from
10 VDC to 15 VDC at less than 100 mA. This remains fairly uniform from a
few memory boards 26 per module to many memory boards 26 per module. Low
power CMOS chips are used, which only draw current during a transition,
and only one memory board 26 and one memory chip is on at any time. Power
supply may be a 12 VDC wall plug power supply, battery, solar power system
or a thermoelectric generator.
Audio output per logic board is approximately 0.5 Watt at 8 Ohms
unbalanced. A suitable matching transformer will provide balanced 600 Ohm
output. The modular concept of the present invention is also applied to
the memory boards 26. They may be removed, installed in any location,
digital messages or programs may be loaded internally or externally and
may be stored individually on the shelf for years, without loss of
program. Low power CMOS static RAM memory chips are used, 8 or less memory
chips per board, along with a single lithium battery 31, shown in FIG. 1,
for memory retention. This technique is covered by U.S. Pat. No.
4,772,873. Lithium battery 31 use complies with UL standards (reverse
current limited). In the power down mode, standby current is less than 10
microamps per board with a 3 VDC Lithium battery. Expected shelf life of a
memory board 26 with a stored program is 8 to 10 years.
Referring to FIG. 1, a memory manager chip 30 manages the memory by
isolating battery 31 when external power is available, and then applying
battery 31 to the memory chips 32 if board 26 loses power. Also memory
manager 30 provides the user warning if battery 31 begins to lose power by
not enabling the user to load a new message.
In order to construct a modular, expandable system, a system buss must be
created that will be expandable, and yet require a reasonable number of
control lines to operate the external system. Referring to FIG. 1, three
busses are defined, one for an external system to control the module, one
for local control of the module 23, and a memory buss 28 for communicating
to and from the memory boards 26 (using a 34 pin edge board connector).
The design philosophy of the memory buss 28 is to create a system that can
access its messages randomly and in any order, not in a serial format like
reel-type tape machines or the previous generation digital recorder. (See
U.S. Pat. No. 4,772,873). Also, the memory bus 28 function should be
independent of the order in which memory boards 26 are connected using
separate channel 21 and memory board 33 numbers. The assignment of the
pins of memory buss 28 is shown below as Table 1. In accordance with basic
digital circuit connections, a line above a description indicates an
active low. For example, at pin 17, updown means that when high, count up
and when low, count down.
TABLE 1
__________________________________________________________________________
MEMORY BUSS
Pin #
Description
__________________________________________________________________________
2 GND.
4 ON. +5 V FROM LOGIC BOARD WHEN RECORDING OF PLAYING.
5
##STR1##
DATA INTO MEMORY CHIPS DURING RECORD SEQUENCE.
7
##STR2##
MEMORY CHIP THE DIRECTION OF DATA. WHEN HIGH, TELLS
MEMORY TO RECORD AS PIN 5 IS STROBED. WHEN LOW, MEMORY TO
PLACE DATA AT OUTPUT PINS. HIGH DURING RECORD AND LOW
DURING PLAY
8 10 12 14
##STR3##
9 SERIAL DATA FROM LOGIC BOARD TO MEMORY BOARD.
11 DATA CLOCK. FROM LOGIC TO MEMORY BOARD, RUNS AT THE
FREQUENCY OF THE SERIAL DATA, USED BY MEMORY BOARDS TO
CONVERT SERIAL DATA TO EIGHT BIT PARALLEL.
13 DATA CLOCK. FROM LOGIC BOARD TO MEMORY BOARD. SAME
FREQUENCY AS PIN 11 BUT ADVANCED IN TIME. USED BY MEMORY
BOARDS TO CONVERT EIGHT-BIT PARALLEL OUTPUT OF MEMORY
CHIPS TO SERIAL FORMAT USED BY CVSD.
15 ADDRESS CLOCK. FROM LOGIC BOARD TO MEMORY BOARD. RUNS
AT ONE EIGHTH THE FREQUENCY OF THE DATA CLOCK. COUNTED
BY MEMORY BOARDS TO PROVIDE ADDRESSING FOR MEMORY CHIPS.
16 18 20 22
##STR4##
17
##STR5##
ADDRESS COUNTERS FOR REVERSE EDITING FEATURE.
19 SELECT OUT. FROM MEMORY BOARD TO LOGIC BOARD. USED BY
LOGIC BOARD TO INCREMENT BOARD NUMBER.
21 HALT. FROM MEMORY BOARD TO LOGIC BOARD. STOPS LOGIC
BOARD FROM PLAYING OR RECORDING.
23 COUNTER STROBE. FROM MEMORY BOARD TO LOGIC BOARD.
COUNTED BY VARIABLE LENGTH CONTROL TO MARK END OF
MESSAGE.
24 5 VOLT REGULATED POWER FROM LOGIC BOARD TO BUSS.
25 LAST BOARD. FROM MEMORY BOARD TO LOGIC BOARD. TELLS
LOGIC BOARD THE LOCATION OF THE END OF THE CHANNEL.
27 SERIAL DATA OUT. FROM MEMORY BOARD TO CVSD OF LOGIC
BOARD
30 RESET. FROM LOGIC BOARD TO MEMORY BOARD. RESETS ADDRESS
COUNTERS ON THE MEMORY BOARD.
32 +12 VOLTS DC. UNREGULATED.
33 +3 VOLTS SECONDARY MEMORY BACKUP VOLTAGE. GROUNDED IF
NOT USED.
34 GND.
PINS 1,3,6,26,28,29 AND 31 ARE RESERVED FOR FUTURE USE.
__________________________________________________________________________
Referring to FIG. 2, each channel 35 has a unique four-bit binary code.
Each memory board 26 dedicated to a certain channel 35 has the same
channel address code and a unique four-bit binary board address code.
Referring to FIG. 1, the board 15 and channel 19 address codes on the
memory buss 28 are compared with the settings on the memory board 26 via
two four bit comparators 25 and 27. This arrangement allows for 16
channels 35 each with up to 16 memory boards 26 in each channel 35, for a
total of 256 memory boards 32. When address codes of both counters 19 and
15 and counters 21 and 33 match, this enables the individual memory board.
For example, a simple system might have two messages to be accessed
randomly. This would require two channels 35 and as many memory boards 26
as needed for each message. The order of placement of the memory boards 26
would not matter. To reduce the number of pins, the data are passed
serially from the logic board 22 to the memory board 26, where it is
converted to parallel before it is placed into memory.
More than one clock is present on the bus 28, they differ in both frequency
and time. Two clocks run at the rate of the data stream, for use by the
serial to parallel and parallel to serial converters. Since each memory
address stores eight bits, the data clock is divided by eight and fed to
the address counters 34. This division is performed on logic board 22, and
then fed through the memory buss 28 (edge pin 15 in Table 1). Two versions
of the data clock are used, one advanced slightly in time with respect to
the address clock and one slightly delayed. The advanced version of the
data clock (edge pin 11 in Table 1) is used during the record sequence, to
insure that the data arrives at the memory chips and is stable before the
chip reads the data bus. The delayed version of the data clock (edge pin
13 in Table 1) is employed to insure that the data is stable before it is
converted to serial and sent back to the logic unit. By displacing
selected clocks in time, the need to resort to a handshaking timing
protocol is avoided. A timing diagram for the clocks of the present
invention are shown in FIG. 3.
With reference to FIGS. 4 and 5, in order to achieve random access memory,
the present invention uses 2 four bit address codes to initialize any
given memory board 26. Five volt power (a logic high) is supplied to the
A=B input of U14, the four bit comparator 25 of FIG. 1, which compares the
channel number address code on buss 28 with the setting of a 16 position
channel switch 21 of the memory board 26. If the address codes match, then
a logic high is supplied in a similar manner to U13, the four bit
comparators 27 shown in FIG. 1, which compares the memory board address
code on the memory buss 28 with the preset 16 position memory board switch
33. Again, if the address codes match, then a memory manager chip, U2, is
enabled.
U2 acts as the memory manager for the memory board 26, performing several
important functions. Beside allowing data to be written to memory board 26
when the memory board 26 is selected, U2 also decodes the three most
significant bits of the address to enable the individual memory chips, and
switches power from VCC or the battery to prevent corruption of the
memory. U2 also will not allow access or memory if the voltage across the
battery falls below a set limit.
The present invention may use an eight-bit serial to parallel converter to
store eight bits of digital system at a time. Memory board 26 may include
a 256K memory organized 8 by 32K. The invention could use memory board 26
organized as 1 by 256K and avoid the serial to parallel process, but eight
bit data buses are currently the industry standard. The memory boards 26
can also accept a variety of memory technologies. CMOS static RAMs provide
instantaneous record and play, while EPROMs and EEPROMs can provide fixed
play only.
Addresses for the memory chips are provided by dividing the address clock
(edge pin 15 in Table 1) by five cascaded fourbit up-down address counters
(shown as 34 in FIG. 1) for reverse as well as forward (U15, U16, U17,
U18, and U19 in FIG. 4). The first 15 least significant binary digits
(A0-A14) are used first 15 least significant binary directly by the memory
chips as addresses. The three most significant digits are decoded by U2 to
enable each memory chip in turn.
During a record cycle, edge pin 7 is set high to enable the memory chips to
read data and enable the serial to parallel converter, U11 in FIG. 5. Data
is passed in a serial format from the logic board 22 to the memory board
26 by edge pin 9, converted to parallel by U11, and strobed into memory
chips (U3, U4, U5, U6, U7, U8, U9 and U10) by pin 5.
During a play | | |
