 |
Description  |
|
|
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention pertains to digital data communication systems and more
particularly relates to methods and apparatus for multiplexing sub-rate
channels in a manner that takes maximum advantage of the switching
system's switching granularity.
2. Description of the Prior Art
State of the art digital data communication switching systems are typified
by the systems described in copending patent application Ser. Nos.
07/103,611, filed Oct. 1, 1987, entitled "High Speed Communication
Processing System", and 07/103,612, now Pat. No. 4,852,089 also filed Oct.
1, 1987, entitled "A Digital Data Communications System". Both of these
applications, hereby incorporated by reference, are assigned to the same
assignee as this invention.
The system taught in the Ser. No. 07/103,612 application is defined as
having m slots of data per frame and n fragments per slot to yield a total
of m.times.n fragments per frame.
For example, the invention taught in the 07/103,612 application permits a
T1 line to be divided up into 24 slots, each 64 Kbps wide, with 8
fragments being defined per slot (each representing 8 Kbps bandwidth).
This yields 192 fragments with an 8 Kbps signalling channel left on the T1
line. Also, bandwidth allocation is contemplated for 2.048 Mbps Inter
Module Links ("IMLs") within a given node, where 32 slots each 64 Kbps
wide are defined (each again with eight 8 Kbps fragments).
Also taught in the referenced applications are means for allocating and
deallocating bandwidth on the communication lines of the system using bit
maps, how to perform allocation in a manner which minimizes call blocking,
contention, etc., and how to interconnect Customer Premise Equipment (CPE)
to the node oriented network via User Interfaces (UI), Network Processors
(NPs), Switch Matrices (SMs), Network Interfaces (NIs), etc., via the IMLs
in a given node.
The systems taught in the referenced applications support the CCITT I.463
standard for multiplexing of sub-rate channels. Also, these systems have
the capability of switching fragment vs. slot packets, i.e., have an
improved switching granularity as compared with the 64 Kbps switch
granularity to which the I.463 standard was designed.
For the illustrative 32 slot, 8 fragments per slot IML bandwidth scheme set
forth hereinbefore, I.463 mandates that sub-rate channels (defined herein
as a 19.2 Kbps channel or any submultiple thereof) be assigned to 64 Kbps
of bandwidth (a whole slot) before being transmitted to the switch.
According to the I.463 standard, two layers of rate adaptation are
performed to condition sub-rate channel data to be transmitted in the 64
Kbps packets.
Given the improved switching granularity and bandwidth allocation
capabilities of systems such as those set forth in the referenced
copending applications, it would be desirable, and it is an object of this
invention, to improve the efficiency of bandwidth usage over the I.463
standard for sub-rate channel bandwidth allocation.
It is also desirable, and a further object of this invention, to be able to
fully use the capabilities a switch, more particularly those switches
taught in the above-referenced applications. Since the inventions taught
in these applications make it possible to switch fragments of less than 64
Kbps, it would be desirable if sub-rate channel assignments were keyed to
the granularity of the switch which in turn is ideally matched to the
choice of fragment size.
For the illustrative example set out above, where the fragment size (8
Kbps) is matched to the switching granularity, an improved I.463
allocation scheme would ideally assign sub-rate channels to fragments (or
integer multiples of fragments), thereby taking maximum advantage of the
system's switch capacity without wasting slot bandwidth.
SUMMARY OF THE INVENTION
According to the invention, methods and apparatus are set forth which
improve the efficiency of bandwidth usage over the CCITT I.463 standard,
for switching systems having a granularity of better then 64 Kbps (e.g. 8
Kbps).
Furthermore, according to the invention, methods and apparatus are set
forth which are capable of performing rate adaptation for synchronized
sub-rate channels in a manner geared to package sub-rate data in fragment
size envelopes (or integer multiples thereof), where the width of a
fragment is matched (ideally equal) to the granularity of the system's
switch.
The preferred embodiment of the invention is taught in the illustrative
context of a switching system having the aforementioned 32 slots per
frame, for each IML, where each slot is 64 Kbps wide, where 8 fragments
are defined per slot, each fragment being 8 Kbps wide, and where the
switch granularity is matched to the fragment width, i.e., is also 8 Kbps
wide. The invention can be generalized to a switching system having m
slots of bandwidth per frame, n fragments per slot and a switch
granularity of x Kbps, where x is less than 64 and each fragment is x bps
wide.
Further yet, in accordance with the invention, (in the illustrative
context), the efficiency of bandwidth usage over the I.463 standard is
achieved by implementing a new rate adaptation scheme in which sub-rate
data channels are assigned to an 8 Kbps fragment, or multiples thereof.
For example, a 2.4 Kbps channel is assigned to an 8 Kbps envelope, 9.6
Kbps is assigned to two 8 Kbps envelopes, etc. Multiple envelopes (each 8
Kbps wide) are then multiplexed effecting a potential 8 fold improvement
over existing methods and apparatus for implementing the I.463 standard.
In the illustrative context, the key is to use the 8 Kbps granularity of
the switch rather then the I.463 standard of assigning sub-rate data to a
whole 64 Kbps slot.
The invention features improved bandwidth usage, efficiency in bandwidth
allocation, and is designed to take advantage of the speed and flexibility
of the systems switching capacity.
The aforestated, and other objects and features of the present invention,
will be understood by those of ordinary skill in the art after referring
to the detailed description of the preferred embodiment and the appended
drawing.
BRIEF DESCRIPTION OF THE DRAWING
FIG. 1 (prior art) is a high-level functional representation of a typical
digital data communication network comprising nodes interconnected by
communication lines.
FIG. 2 is a block diagram of one such node showing a variety of
communication paths both within and outside of a given node.
FIG. 3 depicts the allocation of a communication line into "slots" and
"fragments".
FIG. 4 depicts a bit map organization that is suitable for use with the
present invention.
FIG. 5 depicts, in block diagram form, the prior art CCITT I.463 two level
rate adaption scheme for inserting sub-rate channels into 64 Kbps slots
compared with the rate adaptation scheme taught by the present invention.
FIG. 6 depicts a functional block diagram for a user interface that
supports the improved rate adaption scheme contemplated by the invention.
DETAILED DESCRIPTION
FIG. 1 depicts a typical network consisting of nodes 101, 102, 103, and 104
interconnected by communication lines. Some of the nodes are shown as
having CPE equipment connected to them. (Node 101 is shown connected to
CPE 105, and node 104 is shown connected to CPE 106.) In practice, any of
the nodes may have CPE connected to them.
FIG. 2 shows internal detail of a typical node, comprising a wideband
time-slot switch matrix (110, 120, 130) and a number of dual-ported
network processors (140, 141) connected to each other via 2.048 Mbps
serial links. These internal node paths are the IML links referred to
hereinbefore. The switch matrix permits connectivity between the network
processors, as well as connecting them to the network, via network
interface (NI) means such as NI 111, and to local terminals, PCs and PBXs
(labeled as CPE 115) via other similar serial links and devices such as
user interface (UI) means 12.
Rate adaptation as contemplated by the CCITT I.463 standard, takes place at
the UI level of the network. The prior art process is described
hereinafter with reference to FIG. 5.
FIG. 2 also shows that each network processor is connected to a typical
parallel computer bus 160. The network processors of the system can either
be connected together with a single such bus, or in groups to more than
one such bus. This way the necessary computing resources, such as memory
170, can be connected to the switch processors in a manner traditional to
the computer industry.
The first network processor installed in the system is also programmed to
control the switch matrix connections, such that when particular users in
the network require access to a given network processor, that connection
is carried out by the first network processor upon receiving a command
from that specific user.
On the other hand, asynchronous network processor to network processor
interconnectivity is achieved over the computer bus, such as is required
when two such network processor units are sharing a single communications
processing function such as packet switching. For example, a packet
received by network processor 140 which was destined to network processor
141, if sharing the same bus, simply hands off such packet to network
processor 141 using either DMA or a "mail-slot" technique.
If a node that has been installed with N network processors is showing
inadequate performance, or must then perform additional functionality,
network processor N+1 is added. Furthermore, if the bus bandwidth is
inadequate for all the functions being performed in a single-bus system, a
second computer bus can be added to the system to separate into separate
computing groups the functions that are not interrelated.
FIG. 3 depicts the allocation of bandwidth of a 2.048 Mbps IML
communication line in a switching system assumed, for the sake of
illustration only, to have an 8 Kbps switching granularity. The available
bandwidth is shown divided into thirty-two 64 Kbps slots. (32.times.64
Kbps =2.048 Mbps). Each 64 Kbps slot is further divided into eight
"fragments" of 8 Kbps each.
Not shown in FIG. 3, but contemplated by the invention, is a bandwidth
allocation scheme for other data path frequencies, for example, T1 lines
which could have twenty-four 64 Kbps slots, each with eight 8 Kbps
fragments and a framing/signalling channel of 8 Kbps left over.
According to the invention, the ideal fragment bandwidth is the same as the
maximum switching system granularity. Thus, for a switching system having
a switching granularity of "x" bps, the ideal fragment width is also x
bps. Dividing the fragment width into the frame bandwidth will indicate
the number of fragments possible per frame. These can be grouped into
slots such that each frame has an integral number of slots, m, where each
slot has an integral number of fragments, n.
Returning to the illustrative example, as data begins flowing within a node
(for the IML example) for transmission between devices within the node, a
portion of the available bandwidth on a given link on which that data
appears is inherently taken up by the data.
Bandwidth allocation may be accomplished, as taught in the referenced
applications, using bit maps for each link connected within the node. The
bit maps may be maintained by the network processor (NP) within a memory,
such as memory 170. The bit map for each end of a link contains one bit
position corresponding to each fragment of that link. Each bit position
will contain a ONE to indicate that the corresponding fragment is in use
and unavailable, or a ZERO to indicate that the corresponding fragment is
available. The network processor can thus easily identify available
fragments simply by searching through the bit map looking for ZERO bits.
If more than one fragment is required, there is no necessity to assign
contiguous fragments, as available fragments can be located anywhere in
the link.
By adopting the convention that fragments will be allocated for
transactions originating from one end of a link, from one end of the bit
map, and for transactions originating at the other end of the same link,
from the other end of the bit map, there is no need to pre-allocate to
either, enabling the system to be more efficient when a preponderance of
transactions is originating from one side or the other. The same type of
allocation scheme will enhance performance of the internode T1 lines as
well.
An example of a suitable bit map for a 32 slot per frame IML is delineated
in FIG. 4. This can easily be modified to support 24 slot T1 lines, etc.
Turning to FIG. 5, a comparison of the prior art rate adaptation scheme
used to support I.463, is made against the rate adaption scheme of the
present invention. Although well known to those skilled in the art, a
brief review of the standard I.463 rate adaptation scheme will be
explained for the sake of completeness.
CCITT I.463 implies two layers of synchronous rate adaptation. As
illustrated by FIG. 5, sub-rate data, e.g., an asynchronous 2.4 Kbps
signal, can be input via link 501 from CPE.
The input data is shown synchronized at RAO in FIG. 5. Methods for
synchronizing sub-rate data are well known by those skilled in the art by,
for example, decoding framing bits in synchronized framing bit patterns.
Accordingly, the synchronization shown in FIG. 5 does not constitute a
part of the invention per se.
Once synchronized, CCITT I.463 calls for the performance of two layer rate
adapation at RA1 and RA2 of FIG. 5 (prior art). At the first layer, RA1,
sub-rate data is mapped into envelopes that are integer multiples of 8
Kbps wide. For example, the 2.4 Kbps signal would be "stuffed" into an 8
Kbps envelope, a 19.2 Kbps signal would be stuffed into a 32 Kbps
envelope, etc., per this well known protocol.
The standard protocol goes on to call for a second level of rate adaptation
where each set of envelopes corresponding to a given sub-rate channel
signal, are in turn stuffed into a 64 Kbps slot for transmission to the
switch matrix. This second level of rate adaptation is illustrated in FIG.
5 (prior art) at RA2. The output to the switch at 505 has individual
sub-rate channels embedded in, and taking up, entire 64 Kbps slots.
Since the switch granularity of systems taught in the incorporated patent
applications is better than 64 Kbps (8 Kbps for the illustrated example),
the invention contemplates only 1 layer of rate adaptation as shown in the
lower portion of FIG. 5. Thus sub-rate user inputs on link 511 can be
output to the switch, via links 512, 513 and 514, via RA1 and MUX 520,
without the second layer of rate adaptation called for in the I.463
standard. According to the invention, RA1 performs the same functions in
both the prior art and new approach. RA2 can also be performed as an
option for compatability with other systems.
Also shown in FIG. 5, at 535, is the option, according to the invention, of
performing yet another layer of rate adaptation depending on choice of
fragment size and switch granularity. The illustrative embodiment of the
invention with 8 Kbps fragments (envelopes) and an 8 Kbps granularity
switch, does not require a second level of rate adaptation.
Before going on to the details of implementing the new rate adaptation
scheme, described hereinafter with reference to FIG. 6, it will be useful
to visualize the I.463 protocol as mandating that sub-rate data in the
range of 600 baud to 19.2 Kbps, be inserted into 8 Kbps fragments by means
of an 80-bit frame. Thus, for example, for a 2.4 Kbps signal, 24 data bits
of sub-rate information need to be inserted into an 80 bit frame for the 8
Kbps operating rate. The other 56 bits of information in an 80 bit frame
are filler bits.
It should be noted that the value of t, in a t bit frame, is directly
related to fragment bandwidth. In particular, the relationship is (a) an
n:1 correspondence between the total number of bits chosen for a t bit
frame.
At initialization, a program sequencer can be easily set up to map sub-rate
data bits into any desired location in the aforesaid frame. Also, such a
sequencer can be used to reverse the process, i.e., extract sub-rate
information.
The ability to perform these functions using well known program sequencers
and mapping techniques will add to the understanding of the illustrative
embodiment of the invention to be described immediately hereinafter with
reference to FIG. 6.
FIG. 6 depicts a typical user interface, such as UI 112 of FIG. 2.
The I.463 support facility for a bank of CPE (e.g. CPE 1-N) is shown in
FIG. 6 as Block 601. Multiple I.463 support facility can be located at a
UI, as illustrated by block 602 which is intended to perform the same
function as block 601.
A frame generator, such as device 610 of FIG. 6, is a device well known by
those skilled in the art for generating framing information and does not
constitute a part of the invention per se.
To support the I.463 protocol, frame generator 610 generates a frame clock
(for outputting data) for the 80 bit frames referred to hereinbefore.
Frame Generator 610 is driven off of clock 605, and outputs not only the
frame clock for data output (on link 680), but also control information
and frame overhead data, for use by a program sequencer such as program
sequencer 620.
Program sequencer 620 is depicted in FIG. 6 as having two portions, an
interleave portion and a deinterleave portion.
The program sequencer can be realized by a microprocessor that is
initialized to direct sub-rate channel data into prespecified bit postions
in each 80 bit frame (for interleaving). The same sequencer can be used to
extract sub-rate data in each frame for data destined to the CPE side of
the network (via the deinterleaver).
The deinterleave portion of program sequencer 620 is shown operating in
conjunction with frame detector 640, a device that is also well known to
those skilled in the art. Frame detector 640 determines frame boundries
and enables program sequencer 620 to appropriately remove sub-rate
information from a given frame. Control and frame clock (for input data)
signals are depicted in FIG. 6 as input to program sequencer 620, from
frame detector 640.
The combination of devices 610, 620 and 640 are all that is necessary to
perform both the desired interleaving and deinterleaving in support of any
desired protocol and particularly the I.463 protocol sought to be more
efficiently supported by the invention.
FIG. 6 also indicates how the output of the sequencer, destined for the
switch, can be multiplexed onto an internal UI bus, e.g., bus 650, via
mux/demux device 675, in accordance with a time slot plan stored at device
680 which could be realized by RAM.
UI bus 650 is shown taking output from (and also distributing data to) a
plurality of banks of CPE, and interfacing with IMLs to the switch via
concentrator 699.
What has been described is a rate adaptation scheme that meets all of the
objectives set forth hereinbefore. Those skilled in the art will recognize
that the foregoing description of a preferred embodiment of the novel
methods and apparatus has been presented for the purposes of illustration
and description only. It is not intended to be exhaustive or to limit the
invention to the precise form disclosed, and obviously many modifications
and variations are possible in light of the above teaching.
The embodiment and examples set forth herein were presented in order to
best explain the principles of the instant invention and its practical
application to thereby enable others skilled in the art to best utilize
the instant invention in various embodiments and with various
modifications as are suited to the particular use contemplated.
It is intended that the scope of the instant invention be defined by the
claims appended hereto.
* * * * *
|
|
 |
|
 |
Description |
|
