In an arrangement for combining at least two source signals to a multiplex signal, source signals from independently operating source modules are transmitted to a multiplex module in which they are combined into the multiplex signal in a predetermined manner. An orderly operation of the modules is ensured in that each source module includes at least a memory, a write counter and a read counter. The counters are arranged to operate independently of each other and to generate the addresses when the data are being written into and read from the memory. The arrangement includes a memory for storing the frame-structured source signals at the start of a new frame starting at a predetermined initial address of the memory and for marking the memory address of the end of the frame with a marking bit. The arrangement also includes read logic for reading the source signals from the memory of the source modules under control of a clock signal supplied by the multiplex module, and for transmitting the source signals to the multiplex module. Each source module is arranged to supply a reset signal after the marked address has been read during reading of a frame. The arrangement is adapted to set the read counters of all source modules to the predetermined initial address when the reset signal is eliminated.

In one embodiment, the invention is an apparatus. The apparatus includes a FIFO array having a first plurality of memory elements, each memory element having a predetermined number of bits, the FIFO array having a read pointer. The apparatus also includes a FIFO control register array having a second plurality of memory elements, each memory element of the second plurality corresponding to a memory element of the first plurality of memory elements, the read pointer suitable for accessing the FIFO control register array. The apparatus further includes a control logic block coupled to the FIFO control register array and the FIFO array. The control logic block is to receive a data value of the memory element of the FIFO control register array pointed to by the read pointer. The control logic block is also to signal the read pointer to stall responsive to the data value having a first value.

A pulse stuffing multiplexer apparatus is used in order to carry out multiplexing of these signals. The low order data signal for a single channel is stored into an m-bit memory in accordance with a clock signal obtained by demultiplying the low order clock signal of that channel to l/m to be read out as the high order data signal by a clock signal obtained by demultiplying a common high order clock signal not lower than all the low order clock signals to l/m. When the high order data signal is read out from this memory, an S-th (S.ltoreq.m) of both clock signals is monitored and, when the phase difference therebetween falls within predetermined k-bits (k.ltoreq.m), both demultipliers are reset at the head position of the next frame for both clock signals to be initialized at a predetermined position. In addition, the numbers of the low order clock and the high order clock are counted for each frame and, when the difference therebetween exceeds one bit, the high order clock signal is suppressed at the trailing end of the frame. If the above processing is made to all the channels, then each channel may be inserted at the corresponding position with an appropriate number of stuffing bits for synchronization so that it becomes possible to readily achieve a multiplexed signal by utilizing a multiplexer.

A digital subscriber line circuit for connecting an ISDN subscriber to the trunk side of a digital exchange which comprises an SLD interface operating according to the SLD system. The subscriber line circuit further includes a transfer arrangement for transferring, during a transfer time window, data signals between incoming and outgoing time slots of the SL line of the SLD interface and time slots assigned thereto of outgoing or incoming trunks of the digital exchange. The subscriber line circuit comprises a slip detection means for detecting an incoming or outgoing trunk time slot slipping out of the transfer time window. The slip detection means controls a slip correction means which controls the transfer arrangement in response to the detection of a slip, so that data are skipped in one transfer direction and data are repeated in the other transfer direction.

The invention includes a memory device with a register device to which an output of a multiplexer is connected. The input of the multiplexer is connected to a buffer store. In addition, the memory device includes a synchronization circuit having a control output connected to a control input of the multiplexer. A clock signal output of the synchronization circuit is connected to the clock input of the register device. The synchronization circuit generates and outputs a clock signal to the clock signal output derived from a time profile for a signal on a state input and from a signal on a second clock input. In this way, a data word to be stored in the register device is synchronized to a clock signal on the second clock input, so that data errors are avoided during transfer.