A circuit design method able to design a processing circuit to be small in scale when designing a processing circuit for performing a plurality of different processings on predetermined data, comprising a first step of identifying second processings performing the same processing on the same data among pluralities of second processings forming each of a plurality of first processings when designing a processing circuit for applying a plurality of different first processings on predetermined data and a second step of designing a processing circuit having a processing circuit shared by the plurality of first processings and for performing the second processings identified at the first step.

An image processing system for effecting a predetermined transformation to data representing a multiplicity of pixels which together form an initial image so as to create data representing a multiplicity of pixels which together form a transformed image in which each pixel is formed as a weighted combination of pixels in a respective block of data in the initial image. The system includes a controller operable for each pixel in the transformed image to identify the block of data containing all pixels in the initial image that contribute to the transformed image pixel, to divide the block into a plurality of sub-blocks comprising a plurality of rows of pixel data and plurality of columns of pixel data, and to calculate for each sub-block a set of transformation coefficients depending on the predetermined transformation. A transforming unit applies the respective transformation coefficients to each sub-block of data in order to produce an intermediate value for each sub-block, and an accumulator accumulates the intermediate values from the transforming unit such that once the transforming unit has applied the transformation coefficients to every sub-block in the initial image data block the accumulated value in the accumulator comprises the data defining the transformed image pixel. The controller is arranged for each sub-block to control the transforming unit to apply respective transformation coefficients to each row of pixel data in the sub-block one row at a time in order to produce data representing for each row a partial result and, once transformation coefficients have been applied to every row in the sub-block, to produce data representing a set of partial results, and to apply transformation coefficients to the set of partial results in order to produce the intermediate result.

The logical computer architecture is specifically designed for image processing, and other related computations. The architecture is a data flow concept comprising three tightly coupled components: a spatial configuration processor, a point-wise operation processor, and a accumulation operation processor. The data flow and image processing operations are directed by the control buffer and pipelined to each of the three processing components. The image processing operations are defined by an image algebra capable of describing all common image-to-image transformations. The merit of this architectural design is how elegantly it handles the natural decomposition of algebraic functions into spatially distributed, point-wise operations. The effect of this particular decomposition allows convolution to be computed strictly as a function of the number of elements in the template (mask, filter, etc.) instead of the number of pixels in the image. Thus, a substantial increase in throughput is realized. The logical architecture may take any number of physical forms, including a hybrid electro-optical implementation, and an all digital implementation. The potential utility of this architectural design lies in its ability to control all the arithmetic and logic operations of the image algebra's generalized matrix product. This is the most powerful fundamental formulation in the algebra, thus allowing a wide range of applications.

In an interferometer system, a revolving antenna array is used to sufficiently resolve all ambiguities in determination of frequency and direction of arrival of a wave-front. The frequency and direction of arrival are determined by matching predicted phase difference codes with an actual code measured at the antenna array, utilizing a cross-correlation technique. The number of parameters that can be simultaneously uniquely determined by the system depends on if the antenna array is rotated in planar or conical surfaces, and if the cross-correlation is uni- or multi-dimensional. The antenna array may include more than one baselines to enhance the system sensitivity and finding capacity.

Provided are a loop accelerator and a data processing system having the loop accelerator. The data processing system includes a loop accelerator which executes a loop part of a program, a processor core which processes a remaining part of the program except the loop part, and a central register file which transmits data between the processor core and the loop accelerator. The loop accelerator includes a plurality of processing elements (PEs) each of which performs an operation on each word to execute the program, a configuration memory which stores configuration bits indicating operations, states, etc. of the PEs, and a plurality of context memories, installed in a column or row direction of the PEs, which transmit the configuration bits along a direction toward which the PEs are arrayed. Thus, a connection structure between the configuration memory and the PEs can be simplified to easily modify a structure of the loop accelerator so as to extend the loop accelerator.