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Bus driving and decoding circuit
   
Document Number
US Patent 4967390
Issued Date
October 30, 1990
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Abstract
Bus driving and decoding circuit for validating the decoding of signals put on the bus by said drivers, comprising a plurality of driver elements and a decoder connected to the bus, the drivers being grouped in at least two sets, each implemented in one integrated component having a control input for enabling the opening of the related driver set, the control input receiving an enabling signal which is further input to one driver in each integrated component, so as to obtain at the output of the one driver a validation signal (V1, V2) for the decoder, each validation signal having an intrinsic delay equal to the propagation delay of the related integrated component, the circuit comprising further a delay element, located upstream or downstream of driver elements which generate the validation signals, to provide each of the validation signals with an incremental delay sufficing to cover the propagation delay spread specific to the related integrated component, the decoder being enabled by the joint assertion of the validation signals.
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Number of Claims:
4
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Published
October 30, 1990
Application Number
07/230,636
Filed
August 10, 1988
US Classification
710/305  
Int'l Classification
G06F   13/40   (20060101)   H04L   25/02   (20060101)  
Priority Data
Sep 16, 1987 [IT] 21919 A87
USPTO Field of Search
364/9MSFile  
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