The invention is a method and apparatus primarily for generating pixel representations for the video display of three-dimensional objects projected onto a two-dimensional pixel plane. The scanlines of the pixel plane are associated into N interlaced sets, each set having as members only scanlines having an equivalent vertical pixel location Modulo N. The image memory unit block utilizes both serial and parallel processing. For each color (red, green and blue) and for calculating depths, each image memory unit has a plurality N of Scanline Processors for generating the color or depth data to assign to a given pixel. Each of the Scanline Processors is associated with exactly one of the N sets of scanlines. The image memory units each also include a Master Controller. For certain objects, particularly triangular patches, the Master Controller sets up sequentially each Scanline Processor to render pixels on a specific scanline. As the Scanline Processor is rendered pixels, the Master Controller sets up the next scanline processor, and so on, until the entire patch is rendered. For other constructs, such as non-horizontal vectors, the Master Controller sets up all of the N Scanline Processors simultaneously with all of the data necessary to render the entire vector. Each Scanline Processor determines the location of pixels representing the vector and also calculates data with resepct to each pixel. Each scanline processor only writes to memory that data with respect to pixels of scanlines assigned to the set with which each Scanline Processor is associated.
A video display system includes a frame buffer comprising five sets of one or more VRAMs. An address generator for generating address locations in the frame buffer generates chip select, row select and column select address signals. Because the frame buffer comprises five sets of VRAMs, the generation of the address signals requires divide-by-five operations to be carried out. Accordingly, the address generator includes a unique divide-by-five circuit wherein the division is carried out by a sequence of additions and multiplications. In comparison to conventional systems, the video system of the present invention makes more efficient use of memory capacity in the frame buffer.
A scan converter incorporating a polygon span interpolator with main memory Z buffering. The span interpolator is initiated by instructions from a central processing unit (CPU), and when initiated, the span interpolator inerpolates input color and Z values in parallel. The span interpolator has its own state machine and can, once initiated, operate independent of the clock states of the CPU so that the CPU may process other data. Also, rather than using a dedicated memory as the Z buffer, the Z buffer shares main memory with the CPU. This allows the CPU to send pretranslated initial Z buffer addresses to the span interpolator when the span interpolator is initiated. Subsequent Z buffer addresses and color data addresses may be calculated in parallel with the input color and Z interpolations. Also, since the successive main memory and graphics addresses are known by the software, the memory controller of the invention allows data to be moved directly from main memory to the graphics address without CPU intervention and without having to pass the data through the data caches of the CPU. This greatly improves data transfer efficiencies since the cache penalties present in prior art software scan converters are not present.
An image synthesis apparatus for synthesizing an image using model data including information which defines a three-dimensional structure for an object having a plurality of faces, original image data representing values of pixels respectively belonging to the plurality of faces, and rendering data for converting a three-dimensional image synthesized using the model data and the original image data into a two-dimensional image includes memory divided into a plurality of memory blocks each having a prescribed address unit for storing the model data, the original image data, the rendering data, and synthesized image data representing the synthesized two-dimensional image; an arbiter section including an address space, continuous addresses in the address space being allocated to different memory blocks from one another so as to interleave the addresses in the plurality of memory blocks; and a processor section including a plurality of processors each for accessing the memory means through the arbiter section to synthesize an image of one of the faces of the object based on a part of the model data corresponding to the one face, a part of the original image data corresponding to the one face, and a part of the rendering data corresponding to the one face. The original image data and the synthesized image data are each divided into a plurality of rectangular areas on a two-dimensional coordinate plane, and the plurality of rectangular areas are respectively allocated to the plurality of memory blocks.
When an instruction sequence is divided into a plurality of subsequences and executed by a plurality of painting instruction operators, an effective parallel schedule can be drawn up even if there may exist image elements overlapped one another, thus enabling high-speed painting instruction to be executed. There are provided a control information configuror for giving a directed branch to a subsequence having order dependence upon receipt of subsequences divided by a sequence divider and for excluding, when the subsequence with the branch given has another subsequence having order dependence, the subsequence from the determination targets for order dependence; and a scheduler for processing, when on allocating subsequences to a painting instruction operator at the execution target, the subsequences to be allocated are dependent upon subsequences to be executed outside of the allocatee, after the processing of subsequences at the host is awaited.
An apparatus for utilizing multiple processors to render graphical objects for display including apparatus for storing in memory a list of pixel locations assigned to each of the processors, apparatus for scan converting each received graphical object into pixels, and each processor including apparatus for rendering graphical object pixels at pixel locations assigned to the processor. In addition, a method of utilizing multiple processors to render graphical objects for display including the steps of storing in memory a list of pixel locations assigned to each of the processors, scan converting each received graphical object into pixels, and each processor rendering graphical object pixels at pixel locations assigned to the processor.
