A pulse input apparatus comprises an input circuit for sampling each of input signals for a plurality of channels, an orthogonal memory for storing the sampled signal components of the input signals, sequentially in a direction of its time axis, and a sequencer for reading the sampled data items from the orthogonal memory, in a direction orthogonal to the time axis, to obtain a code representing the time at which the input signal has changed, in accordance with the command read out of a command memory. The sequencer measures the time of the change from the code and the present time, and then adds the measured time to the corresponding command, and stores the time into the command memory.
A method and apparatus for interfacing a serial data signal having an associated data clock signal to a circuit, which is clocked at a slightly higher local clock frequency, employs a D-type flip-flop to sample the data clock signal at the local clock frequency. Another D-type flip-flop stores the sample previous to that stored by the first flip-flop and on the basis of these two stored samples a decision is made as to which clock pulses of the local clock should be passed by a gate to form a modified clock signal. This modified clock signal is used to clock a third flip-flop which reads in the bits of the data signal. The modified clock signal can then be used to clock the data through a shift register so that it can be converted to a parallel format.
A synchronization circuit synchronizes asynchronous parallel byte words input data with synchronous parallel byte output data so as not to glitch or interrupt required regular flow of synchronous data to end user devices.
A neural network component includes a plurality of inputs, at least one processing element, at least one output, and a digital memory storing values at addresses respectively corresponding to the at least one processing element, wherein the at least one processing element is arranged to receive a value from the digital memory in response to an input signal, and is instructed to execute one of a plurality of operations by the value that is received from the digital memory.
A pulse input device has a standard time generator for outputting standard time information by counting a system clock signal; an input circuit for sampling input signal information from a plurality of channels in synchronization with the standard time information at a predetermined period; a memory for storing the input signal information sampled by the input circuit; a command memory for storing a plurality of instruction commands; and a controller for scanning the instruction commands stored in the command memory to successively execute the instruction commands, for repeating the scanning operation of the instruction commands, and for controlling operations of the device. The controller outputs a designation signal having a period of a predetermined time for designating an execution starting time obtained by counting the system clock signals, so that the period of the execution starting time for each of the instruction commands becomes a constant rate in the successive command scanning operation for successively executing each of the instruction commands in synchronization with the designation signal, and the period of the predetermined time is set based on the instruction command having the longest execution time.
A method for communication between multiple processors using registers that are accessed by four register select lines which are translated from the original system address. The address translation is performed off of the main processor board to reduce loading effects on the local bus and reduces the pin count of processor board. A signal representing which of the processors is currently active is used as a pseudo address line for the purpose of the translation. The original addresses of the I/O registers may be either input/output or memory mapped.
