A gain memory cell circuit includes a storage capacitor connected between a storage node and ground, a write word line, a read word line, a second capacitor capactively coupling the read word line to the storage node, a read transistor having its source/drain path coupled between the bit line and ground and having its gate coupled to the storage node, and a write transistor having its source/drain path coupled between the storage node and bit line and a control electrode connected to the write word line.
In a gain-cell type semiconductor memory element having a first MOSFET and a second MOSFET, the sources of the first and second MOSFETs are connected to a bit line, the drain of the first MOSFET and the gate of the second MOSFET are connected to each other to serve as a charge storage region, the gate of the first MOSFET is connected to a write word line, the drain of the second MOSFET is connected to a power supply line, and the channel region of the second MOSFET is capacitively coupled via an insulating layer with a read word line thereby to receive substrate biasing by capacitive coupling from the read word line.
An analog memory circuit of the present invention includes: a recording circuit for recording and holding an input analog signal as a charge and for reading out the analog signal after deterioration of the analog signal caused by leakage of the charge in a holding operation is eliminated; a selecting circuit for controlling an operation of the recording circuit; and a driving circuit for supplying a predetermined constant voltage to the recording circuit, wherein the recording circuit includes: an input/output terminal for inputting and outputting the analog signal; a first capacitor having a first electrode and a second electrode, for recording and holding the analog signal as the charge; and a second capacitor connected between the second electrode of the first capacitor and a reference potential, for holding a charge leaked from the first capacitor, and wherein an amount of charge corresponding to an amount of leaked charge held in the second capacitor is restored to the first capacitor with predetermined timing.
A DRAM having a data preset function is disclosed. A memory cell includes connectors which are formed of contact holes or through holes and which can be selectively formed in order to program preset data. For example, when preset data "0" is programmed, connectors are formed, and connector 17 is not formed. When a data precharge signal of a high level is applied, a transistor is turned on and as a result, a data storage capacitor is discharged. In other words, predetermined data is written into capacitor. Thus, the DRAM having the data preset function is provided.
This patent discloses a split-gate flash memory cell having a vertical isolation gate and a process for making it. The inventive cell has better control and a denser memory array than conventional cells. By use of a vertical isolation gate a smaller cell size is obtained. The memory cell has a floating gate transistor formed in a substrate having a channel extending underneath a floating gate, and a vertical isolation transistor formed in the substrate having a channel parallel to a trench holding a portion of a polysilicon control gate and orthogonal to the channel of the floating gate transistor.
A memory circuit incorporating a current-mirror type amplifier which directly amplifies a varied potential of a pair of bit lines. As soon as the word line goes High, the current-mirror type amplifier is simultaneously activated to amplify a minimal difference (100 mV) of potential between these bit lines. Data signal outputted from the current-mirror type amplifier is then transmitted to a read-only signal line. As a result, data is quickly read out before a built-in sense amplifier completes amplification, thus quickly achieving an accessing operation at extremely fast speed.
