Device for processing telephonic signals for putting in communication a plurality of subscribers by means of a telephone exchange employing circuits on cards of subscribers, comprising digital signal processing devices adapted to create filtering functions for the purpose of connecting the subscribers to one another, characterized in that it comprises, associated with said telephone exchange, at least two digital signal processing devices (15, 16) common to a plurality of lines of subscribers (10a-10n, 11a-11n), each connected, on one hand, to the telephone exchange (17) and, on the other hand, to a group of lines of subscribers and adapted to process the signals coming from said corresponding groups of lines of subscribers in shared time so as to effect calculations of filtering functions associated with the various subscribers in accordance with frequencies assigned to the calculations of filter stages adapted to constitute said filtering functions and the chronology of reception of said signals of subscribers.
A method and apparatus for preprocessing digital voice data enroute to or from a Telephone's CODEC. The apparatus supports a CODEC directly connected to an internal bus and using a separate CODEC clock and sync signal to control transfers between a telephony link/internal bus interface and the CODEC. According to an embodiment of the present invention, an auxiliary processing device (connected to the internal bus side of the phone) is provided with means to process the digital voice information before sending it uplink or to the CODEC. This is accomplished without changing the position of the incoming voice field.
The current invention provides apparatus for relieving congestion associated with interfacing voice-band data, and broad-band data, with a network such as the public switched telephone network (PSTN). A hierarchical system for converting digital transmissions on a network between a first protocol and a second protocol is disclosed. The transmissions are generated by data terminals communicating in a third protocol with the network. The hierarchical system includes: interface units, a local processor, a first remote processor and a first controller. The interface units are each coupled to corresponding ones of the data terminals and each signal a call session with the corresponding data terminal. The interface units convert the transmissions from the data terminal in the third protocol to the second protocol. The local processor is switchably coupled to the interface unit and communicates with the network. The local processor converts digital transmissions from the second protocol to the first protocol. The first remote processor is coupled to each of the interface units and communicates with the network. The first remote processor converts digital transmissions from the second protocol to the first protocol. The first controller detects the signaling from the interface units corresponding to the call session and allocates to an available one of the local processor and the first remote processor a conversion of digital transmissions associated with the call session from the second protocol to the first protocol. In an alternate embodiment of the invention, a hierarchical system includes remote control and processing capability.
A method of processing a digital signal wherein multiple signal values are simultaneously operated upon in a single register. The register is not segmented in hardware, but is segmented by operation of a controlling computer software program. The controlling computer software arranges the digital signal in a computer memory in such a manner as to permit the register to be loaded with a plurality of digital samples, each having a precision less than the total precision available in the register. The method may include steps to partially compensate for errors introduced by carries from one segment of the register to another segment of the register, when necessary.
A digital signal processor (DSP) architecture which allows the DSP Multiply-Accumulator (MAC) to be used for special fixed functions during those times when the programmable portions of the DSP are not using the MAC circuitry. During the idle times, the DSP processor gives control of the MAC to the fixed function circuit. The fixed functions provided by the fixed function circuit can include digital filters, including a Finite Impulse Response filters (FIR), an Infinite Impulse Response (IIR) filter, or an oversampling filter associated with a sigma-delta converter. The DSP may, under program control, set up specific parameters for the fixed function, provide parameters to the fixed function parameter memory, or obtain results from the fixed function. Parameters for the fixed function circuit include the type of filter, the number of taps and the filter coefficients. For a decimation filter, the fixed function parameters can also include the decimation factor.
In order to automatically calculate an operational sequence of processes that determine an output value from at least one input value, a multitude of processes (P1 P8), whose inputs are provided with at least one of the attributes: input value of the same calculation cycle (PRE), input value of the preceding calculation cycle (POST), input value from any calculation cycle (ANY), are arranged in such a manner that a process, which does not have any input with the attribute input value of the same calculation cycle (PRE), is determined as the first process of a calculation cycle and, in successive analogous steps, determines a quantity of possible sequences.
