A SIMD machine employing a plurality of parallel processor (PEs) in which communications hazards are eliminated in an efficient manner. An indirect Very Long Instruction Word instruction memory (VIM) is employed along with execute and delimiter instructions. A masking mechanism may be employed to control which PEs have their VIMs loaded. Further, a receive model of operation is preferably employed. In one aspect, each PE operates to control a switch that selects from which PE it receives. The present invention addresses a better machine organization for execution of parallel algorithms that reduces hardware cost and complexity while maintaining the best characteristics of both SIMD and MIMD machines and minimizing communication latency. This invention brings a level of MIMD computational autonomy to SIMD indirect Very Long Instruction Word (iVLIW) processing elements while maintaining the single thread of control used in the SIMD machine organization. Consequently, the term Synchronous-MIMD (SMIMD) is used to describe the present approach.

Video display apparatus having multiple processors for operation in parallel, each processing a respective complete video image in the sequence of video images (fields or frames) which form a video picture, the processing being in accordance with a selected signal processing algorithm. The algorithm may be one which simulates a signal processing circuit design which is to be evaluated, so that the effect of changes in circuit design can be displayed in real time. The signal data for each of the sequential video images is assembled into data packets in successive equal time slots, which are transmitted downstream on a data bus along which are a succession of data processors. The headers of the packets for a given image identify a serially corresponding processor to which such image is assigned, and such packets are processed by the assigned processor in accordance with the selected algorithm. If the processing time of each processor corresponds to the time period of N images, then by using N processors the nth processor will have completed processing of the nth complete image by the time of arrival of the (N+n) th image. Each series of N images can therefor be cyclically assigned to the series of processors, and are processed in parallel in real-time. Provision is made for inter-processor communication when the algorithm has temporal effects on the video picture which necessitate FIR or IIR filtering in order to display such effects.

The present invention provides for an on-chip communications method with fully distributed control combining a fully-pipelined, fixed-latency, synchronous bus with a two-level arbitration scheme where the first level of arbitration is a framed, time-division-multiplexing arbitration scheme and the second level is a fairly-allocated round-robin scheme implemented using a token-passing mechanism. Both the latency and the bandwidth allocation are software programmable in real-time operation of the system. The present invention also provides for a communications system where access to a shared resource is controlled by the above communications protocol. Access to and from the shared resource from the subsystem is through a bus interface module. The bus interface modules provide a level of indirection between the subsystem to be connected and the shared resource. This allows the decoupling of system performance requirements from subsystem requirements. Communication over the bus is fully memory mapped.

An electronic device for transmitting data to an audio visual device in a domestic data communications network system includes a communications arrangement for transferring a memory access designating frame having an access type and a memory storing address stored in a data field thereof precedent to a read data requiring frame or a write data transferring frame. The communications arrangement has a device controlling part, a data transmission processing part and a communications unit for accomplishing easy realization of processing and transmission of a frame format and data common to the master and slave device.

An image processor has a plurality of unit processors, each of which are assigned specific non-contiguous frame regions. All of the unit processors simultaneously start processing input partial image signals after all of the signals corresponding to the assigned frame regions have been fetched.