A fault tolerant clock system in which synchronization of the clocks continuing to operate after a fault occurs is maintained within a skew limit. The clock system includes a plurality of clock channels (10), each including a clock unit (12) and an isolation port (14). A local clock signal produced by a crystal oscillator (16) is enabled to provide a clock channel output signal while a counter (24) in the clock unit accumulates a predetermined number of local clock pulses. After the predetermined number is reached, the counter disables the clock channel output signal and produces a sync pulse, which is input to a voter block (48). In response to the second sync pulse to be received from each of the clock channels, each voter block produces a load pulse signal that is input to the isolation port of that clock channel. Corresponding isolated load signals are produced by the isolation port and provided to voter blocks (72) in each of the clock units. The voter blocks respond to the second isolated load signal to be received, producing a load enable signal that is input to the counter. Upon receipt of the load enable signal, the counter resumes counting and again enables the clock channel output signal, in synchronization with the other clock channel output signals. Up to N simultaneous faults may be sustained in the clock system, without loss of synchronization in the clock channels that continue to operate properly, so long as 2N+1 clock channels are provided.
A storage cell of an integrated circuit is operable in a radiation environment to capture and store at predetermined time intervals a time sample of a data input signal. A signal representative of the stored data sample for each time interval is generated at an output of the storage cell. At least three data capturing circuits operate to capture and store a time sample of the data input signal at each predetermined time interval, the stored data sample of each circuit being generated correspondingly at an output thereof. Coupled to the outputs of the data capturing circuits is a circuit for generating a signal representative of a stored data sample selected from at least two of the circuit outputs. Also coupled to the data capturing circuits is a circuit for causing each data capturing circuit to capture a different time sample of the input data signal from the other data capturing circuits over each predetermined time interval.
A fault tolerant data processing system which provides single fault Byzantine resilience which system uses a number of fault containment regions each of which includes at least one processing element. The fault containment regions of the system are arranged to utilize a shared memory, each of such regions including a portion of the shared memory. The shared memory portion of each fault containment region provides communication with the shared memory portions of each of the other fault containment regions. A shared memory portion includes an encoder for encoding a data byte from the processor in the region into a number of data byte symbols from which the data byte can be reconstructed. The data byte symbols can be stored in the shared memory portion of the region and can be transmitted to one or more of the shared memory portions of the other fault containment regions.
This invention relates to fault-tolerant real-time clock capable of withstanding n-faults, including Byzantine faults. In particular, the instant invention produces redundant clock signals which have low skew with respect to each other, operate with extremely high accuracy, and can be constructed without use of analog electric components, with the exception of oscillators. The present fault tolerant clock is composed of three types of electrical subcircuits coupled together: oscillators/counters, sequential edge voters, and regular voters. Each of these subcircuits can be duplicated and coupled appropriately as needed to form a clock mechanism tolerant of any number of faults in the clock circuitry while maintaining an extremely precise timing mechanism suitable for accurately integrating and differentiating signals with respect to time.
A multiple-fail-operational fault-tolerant clock having a plurality of interconnected and identical clock modules, that provides a fault tolerant clock signal despite some clock module failures. The clock incorporates fault-tolerant operational diagnostics so that a working clock module may be voted for supplying the output clock signal.
A communication system (105) utilizes the global positioning system (GPS) to maintain a high degree of accuracy of synchronization of base-stations (115-116). When the GPS signal (106, 107, or 108) is absent, the communication system (105) employs an alternate signal (110-113), such as a WWVB, LORAN-C, and MSF signal, to provide redundant synchronization of the base-stations (115-116). To achieve the degree of synchronization accuracy provided by the GPS signal (106-108), the communication system (105) characterizes the alternate signal (110-113) by utilizing the GPS signal (106-108) when the GPS signal (106-108) is present. When the GPS signal (106-108) is absent, the characterized alternate signal is then employed such that synchronization of the base-stations (115-116) is transparent to the base-stations (115, 116). Use of the GPS signal (106-108) to characterize the alternate signal (110-113) also allows the characterized alternate signal to provide the same degree of accuracy as that of the GPS signal (106-108).
