A system and method are provided for encoding and decoding data in a video processor system wherein image data values represent a plurality of successive images. A current image is stored into a block of memory locations and later read from the block of memory locations, encoded and transmitted. In addition to being transmitted, the encoded data values are also decoded in order to provide companded image values. The companded image values are then stored into the same block of memory locations as the current image. The data values representing the current image are simultaneously read from the memory block while the companded values are being stored into the same memory block under the control of a number of pointers and a number of synchronization flows. Additionally, the companded data values are simultaneously read from the same memory block for the purpose of performing motion estimation. The system of the present invention therefore permits the same block of memory locations to be used for dynamically storing and reading a plurality of images.

A digital television system (10) System (10) may receive a video signal at composite video interface and separation circuit (16). The video signal is separated into component form by composite video interface and separation circuit (16). The component video signals are converted to digital component video signals in analog to digital converter circuit (18). Line slicer (14) divides each line of digital component video signal into a plurality of channels such that each channel may be processed in parallel by channel signal processors (22a) through (22d). Each channel signal processor (22a) through (22d) may provide two lines of output for each line of video input. The processed digital component video signals may be formatted for displays (26a) through (26c) in formatters (24a) through (24c). Each formatter (24a) through (24c) may comprise a plurality of first in-first out buffer memories (34a) through (34j). One of each channel signal processors (22a ) through (22d) may be coupled to two of first in-first out buffer memories (34a) through (34j). Additionally, each formatter (24a) through (24c) may comprise channel data format units (38a) through (38d), each associated with a channel of, for example, display (24a). Channel data format units (38a) through (38d) are coupled to appropriate of first in-first out buffer memories (34a) through (34j) via multiplexers (36a) through (36d). Each formatter (24a) through (24c) may remove overlap between channels of system (10) and may format the processed video signal into appropriate channels for displays (26a) through (26c).

An image data memory control unit for storing the image data of a plurality of planes in a multiport video memory including a memory component having a random port for reading and writing data therethrough in response to input address signals and a register component having a serial port for outputting data that have been stored in the memory component serially in sequence from the lower address in synchronicity with input clock signals, comprises an image processor for outputting address signals in which the most significant bit portion is a plane recognition bit portion that recognizes the plurality of planes, and for outputting the image data of the plurality of planes therethrough to the multiport video memory in response to the address signals; and address conversion unit for converting the address signals output from the image processor so that the plane recognition bit portion is moved to the least significant bit portion, and the remaining bits are shifted to higher significant bits following the least significant bit portion.

A method for storing video signal data of at least a partial frame in standard memory components includes providing standard memory components with 2.sup.m possible memory addresses, addressing b pixels with x address bits and separately addressing z lines with y address bits through picture addresses, and selecting b<2.sup.x, z<2.sup.y, and m, b, z, x and y as positive integers 2.sup.m is selected to be as small as possible but greater than the product of b and z. The x address bits and y address bits are recoded utilizing bit combinations not occurring in the picture addresses for uniquely assigning each occurring picture address its own memory address. A circuit configuration for performing the method includes a memory device having memory address input terminals for addressing 2.sup.m possible memory addresses, a data input terminal, and a data output terminal. A control device assigns picture addresses to video signal data and controls memorization of the video signal data. The control device has picture address terminals carrying picture addresses with separate x address bits for pixel addressing and y address bits for line addressing. A recoding apparatus is connected between the picture address terminals and the memory address input terminals for uniquely assigning each picture address its own memory address. A device is provided for reading out video signal data from the memory device.

The present invention relates to a video display processor comprised apparatus for receiving digital input signal components of a signal to be displayed, apparatus for converting the components to a desired format, apparatus for scaling and blending the signals in the desired format, apparatus for outputting the scaled and blended signals for display or further processing, and an arbiter and local timing apparatus for controlling the apparatus substantially independently of a host CPU.