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BACKGROUND OF THE INVENTION:
1. Field of the Invention
The invention relates to battery powered computer systems, and more
particularly, to circuits and methods for reducing the power consumption
of the computer system.
2. Description of the Prior Art
Portable computer systems are rapidly developing the capabilities of
conventional desktop or floor mounted personal computer systems. Hard disk
units are being integrated into portable computers because of the large
amounts of information being processed and the large size of many
applications programs. At east one floppy disk unit is integrated in the
vast majority of portable computers, even if a hard disk unit is
installed, to allow loading of information and use of applications
requiring key disks and of diagnostic programs. Modems have been
integrated into portable computers for some time to allow communications
and information transfer between the user and a remote location, for
example, the home office. The displays in the portable computer systems
are becoming much more elaborate and readable. The pixel count on the
standard liquid crystal displays (LCD's) utilized is increasing, as is the
viewing angle. The use of backlighting allows use of LCD's in low light
environments and improves the contrast ratio of the display. More complex
circuitry is being installed in the portable computers to support these
improved peripheral devices and to support the increased speeds and
capabilities of the microprocessors utilized in the portable computer
systems.
The various peripheral devices and high speed circuitry mentioned above
consume large amounts of power when operating. This has made it very
difficult to provide all the possible functionality available and yet have
an acceptable battery life when the portable computer system is battery
powered, so that it can be used in locations where alternating current is
not available. Using CMOS components helped reduce the power consumption
of the circuitry, but even the use of CMOS components is insufficient at
the clock speeds and performance levels of available circuitry. Therefore,
a dilemma arises whether to provide lesser functionality with longer
battery life or greater functionality with lesser battery life or even no
battery operation.
Various alternatives were tried to resolve the problem. For example, the
IBM Corporation PC Convertible included a switch which the user could
press to place the computer system in a standby mode, but the PC
convertible was relatively simple, with a low level of functionality as
compared to what is currently available and the requirement of a user
action limited its use to circumstances where the user remembered to
depress the switch. Blanking the display after a period of keyboard
inactivity saved power as well as prolonged the life of the display and
was widely utilized. A hard disk unit was developed which reduced the
power used by the controlling electronics by utilizing only certain
portions of the track for servo information and turning off the read
channel circuitry until just before a servo burst was expected.
Additionally, a programmable value could be provided to the hard disk unit
so that after a given inactivity interval defined by this value, the hard
disk unit was allowed to spin down and all but some interface circuitry
was shut down. While these alternatives did provide some relief, they were
not complete solutions to satisfactorily resolve the dilemma and design
tradeoffs still were forced to occur.
SUMMARY OF THE INVENTION
A battery powered portable computer system according to the present
invention determines when the computer system is not in use by monitoring
peripheral device activity and shutting down the system after a given
inactivity period, thus entering a standby mode. The entry is not
dependent on an action by the user, but occurs automatically.
The system monitors accesses to the hard disk unit, the floppy disk unit,
the keyboard, the serial ports and the printer to determine if the system
is active. If so, a timer is restarted on each access. If the timer counts
down to zero, then the system is considered inactive and power is removed
from the hard disk unit, the floppy disk unit, the LCD, and miscellaneous
circuitry, and the system clock provided to the microprocessor and other
portions of the circuitry is stopped. Stopping the clock dramatically
reduces the power consumed by the circuitry because CMOS devices, which
are utilized in the preferred embodiment, consume very little power at
zero frequency operation.
To bring the computer system out of this standby mode, the user depresses a
switch which starts the wake up operation. However, if the charge
remaining in the batteries is below a given level referred to as low
battery 2, the system will not wake up or leave standby operation. This
prevents the data in the machine from being lost when the powering up
process consumes the remaining energy in the batteries.
The inactivity interval timer is set at a first value when the computer
system is turned on, with the interval value changeable by the user
thereafter. The interval value is reduced automatically when the battery
charge reaches a level referred to as low battery 1 and is reduced to a
very small value when the battery charge reaches low battery 2. The
interval is also set to a very short interval when the user presses the
standby switch while they system is operating. The inactivity interval is
not utilized when the computer system is powered from an alternating
current (AC) source, such as an AC adaptor/battery charger or mating
expansion unit.
This invention allows the battery powered operating period of the computer
system to be greatly extended, thus allowing the use of advanced
capabilities and functions while having a satisfactory battery operated
operating interval.
BRIEF DESCRIPTION OF THE FIGURES
A better understanding of the invention can be obtained when the following
detailed description of the preferred embodiment is considered in
conjunction with the following drawings, in which:
FIG. 1 is a schematic block diagram of a computer system incorporating the
present invention;
FIGS. 2, 3, 4 and 5 are more detailed schematic logic diagrams of portions
of the computer system of FIG. 1;
FIGS. 6A, 6B and 6C are flowchart illustrations of sequences for preparing
the computer system of FIG. 1 for utilizing the present invention; and
FIGS. 7A, 7B and 7C are flowchart illustrations of a sequence for
controlling portions of the computer system of FIG. 1 according to the
present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
Referring now to FIG. 1, the letter C generally represents a computer
system incorporating the present invention. An address and data bus 20 is
the primary communication pathway in the computer system C. Attached to
this address and data bus 20 are numerous units, including a central
processing unit or microprocessor 22, memory devices 24, a CMOS memory and
clock 26, a direct memory access (DMA) controller 28, a serial interface
29, a modem 30, a floppy disk controller 32, a hard disk controller 34, a
parallel printer interface 36, a display controller and adaptor 38, a
keyboard interface 40, and power control logic circuitry 42.
The microprocessor or CPU 22 is preferably a CMOS version of the Intel
Corporation 80286 microprocessor. The CMOS version of the processor is
preferable because of its lower power consumption while operating and
because it is a fully static device which is capable of operating with a
zero frequency clock and yet not losing any data. The memory devices 24
are composed of read-only memories (ROM's) and random access memories
(RAM's). The RAM's in the preferred embodiment are preferably pseudostatic
devices which contain their own individual refresh circuitry so that other
portions of the computer C need not be activated to provide refresh
signals to the memories during low power consumption modes. The CMOS
memory 26 is preferably powered by its own separate battery 44 so that
certain critical or useful system configuration information can be
retained at all times and not be stored on disk units or prompted for each
time the computer system C is turned on. The serial interface 29 is
preferably an asynchronous interface and includes the customary universal
asynchronous receiver transmitter (UART) devices and appropriate buffering
and level shifting circuitry. The modem 30 also contains the appropriate
UART to perform the parallel/serial conversions necessary and contains the
necessary tone developing and receiving circuitry and telephone line
interface circuitry to allow the modem 30 to communicate over conventional
telephone lines.
The floppy disk controller 32 interfaces to a floppy disk 46 drive. The
hard disk controller 34 is coupled to a hard disk unit 48. The hard disk
unit 48 in the preferred embodiment is of a design as indicated in the
prior art section as being appropriate for low power consumption
applications. The display controller and adaptor 38 is coupled to a liquid
crystal display (LCD) 50. The LCD 50 in the preferred embodiment includes
a backlight. The display controller and adaptor 38 includes the capability
to bank the LCD 50 after a period of time has elapsed without a keystroke
entry, to preserve the life of the LCD 50 and to reduce power consumption.
In the preferred embodiment the display controller and adaptor 38 is
designed to be compatible with a standard referred to as the VGA standard.
The display controller and adaptor 38 is designed to be optionally
connected to an external high quality color monitor and therefore includes
the necessary circuitry, such as a RAMDAC or color palette device, to
allow the utilization of the monitor. The keyboard interface 40 connects
the CPU 22 to a keyboard 52, which includes a dedicated microprocessor for
key scanning functions and communication with the keyboard interface 40
and has a line to receive a power down signal from the power control logic
circuitry 42.
A power control logic circuitry 42 performs the functions of monitoring the
address and data bus 20 and determining the intervals since the last
access to the serial port 29, the modem 30, the hard disk controller 34,
the printer interface 36 or the keyboard interface 40 or appropriate
accesses to the floppy disk controller 32. The power control logic
circuitry 42 monitors the state of a line called ACPWR, which line
indicates whether the power which is being consumed by the computer system
C is being supplied by an alternating current source or whether the
computer system C is operating off of its internal batteries 54. The power
control logic circuitry 42 monitors a line referred to as the SWN0* line,
which is pulled up to a high level by a resistor 56 and which is connected
to ground by a standby switch 58. The presence of an asterisk after a
signal or line indicates that the signal or line is an active or true low
signal or line, rather than the conventional active or true high state.
The standby switch 58 is a normally open switch which is momentarily
closed by the user and is used to place the computer system C in standby
mode or wake the computer system C up from standby mode. Additionally, the
power control logic circuitry 42 monitors the status of two signals
referred to as LOWBAT1 and LOWBAT2, which are developed by the battery
voltage logic 60 which monitors the charge remaining in the batteries 54.
If the charge is below a first given level indicating that approximately
only 10% of a full charge remains, this is the LOWBAT1 level and the
LOWBAT1 signal is set to reflect this state. If the batteries continue to
be discharged, they eventually reach a second lower energy level, which is
referred to as the LOWBAT2 level and the LOWBAT2 signal is set
accordingly. The LOWBAT2 level is reached when approximately only 5% of a
full charge remains in the batteries 54. These level signals are provided
to indicate to the user warning levels relating to the amount of time
available before depletion of the battery and to indicate to the computer
system C the advisability of operating at full power levels.
The power control logic circuitry 42 has a number of outputs. Two outputs
are used to drive the power light emitting diode (LED) 62 and the battery
state LED 64. The power control logic circuitry 42 drives the power LED 62
in a continuous fashion if the computer system C is turned on and not in
standby mode. If the computer system C is in standby mode, indicating that
it is in its low power consumption mode and is halted, the power LED 62 is
flashed to provide an indication to the user. The battery LED 64 is off
when the battery is sufficiently charged, begins flashing at a first
relatively slow rate of 1 Hz when the LOWBAT1 condition exists and flashes
at a higher rate, for example a 2 Hz rate, when the LOWBAT2 condition
exists. These various battery level warnings are visual indicators to the
user as to the remaining energy in the batteries. The power control logic
circuitry 42 has a series of outputs which are connected to several field
effect transistors (FET's) 66, 68 and 70, which are used, respectively, to
control power to the modem 30, the hard disk 48, and the LCD 50.
The power control logic circuitry has an output referred to as the SLEEP*
signal which is provided to an inverter 72 to produce the SLEEP signal.
The presence of an active or true SLEEP signal indicates that the computer
system C is in sleep or standby mode. The SLEEP signal is connected to the
keyboard 52 to cause the keyboard electronics and microprocessor to go
into a low power condition. Additionally, the SLEEP signal is provided to
an FET 74 to remove power from various miscellaneous circuitry 76 in the
computer system C. It is to be noted that power is not removed from many
portions of the computer system C, such as the CPU 22 and the memories 24.
The SLEEP signal is provided to the memory devices 24 to cause the RAM's
to enter their pseudostatic mode and begin controlling their own refresh.
The SLEEP signal also is inverted and provided to the input of a two input
clock AND gate 78 used to disable the system clock. A crystal 80 is
connected to a clock generator circuit 82 which produces a CLK signal
which is provided to the power control logic circuitry 42 for its internal
clocking functions and which is provided to the second input of the clock
AND gate 78. The output of the clock AND gate 78 is the system clock which
is used by the CPU 22 and other portions of the computer system C for
clocking functions. Thus when the SLEEP signal is at a high state, the
output of the AND gate 78 is at a low state, thereby stopping the system
clock and causing the clocked CMOS circuitry located in the computer
system C to go into a very low power state. Alternatively, if it is
desired that the system clock be stopped at a high level, the clock AND
gate 78 can be replaced by an OR gate and the SLEEP signal directly
applied. For details regarding stopping the clock signal to the CPU 22,
refer to Harris Corporation ADC 286 Hardware Reference Manual, p. A-6, the
contents of which are incorporated by reference herein.
The CLK signal developed by the clock generator circuit 82 is tied to the
clocking input of a D-type flip-flop 100 (FIG. 2). The D input to the
flip-flop 100 is provided by the output of a two input NOR gate 102. The
inputs to the NOR gate 102 are the SLEEP* signal developed by the power
control logic circuitry 42 and the SWN0* signal provided to the power
control logic circuitry 42. The NOR gate 102 is used to indicate and
receive the depressing of the standby switch 58 when the system is in
standby mode to begin the wake up procedure. When both signals are in a
low state indicating that the computer system C is in standby mode and the
user desires to wake up the computer system C, the low signal present at
the D input is clocked to the Q or noninverting output of the flip-flop
100 on the next rising edge of the CLK signal. The noninverted output of
flip-flop 100 is provided to the D input of a D-type flip-flop 104. The
clocking signal of the second D-type flip-flop 104 is also the CLK signal.
The inverted output of flip-flop 100 and the non-inverted output of
flip-flop 104 are inputs to a two input NAND gate 106. The output of the
two input NAND gate 106, whose active condition is a low pulse one CLK
signal cycle in length after the standby switch 58 is released, is
provided to one input of an AND gate 108, whose output is applied to the
reset input of a sleep D-type flip-flop 110.
The sleep flip-flop 110 is one bit in a register referred to as the power
control register 109. The power control register 109 contains the storage
elements which control and indicate which of the peripheral devices and
the system are powered on. The power control register 109 is readable by
the computer system C and writeable by the computer system C. The various
additional storage elements comprising the power control register 109 are
a modem D-type flip-flop 112, a RAMDAC d-type flip-flop 113, a hard disk
D-type flip-flop 114, and an LCD D-type flip-flop 116. All of the
flip-flops in the power control register register 109 have their D inputs
coupled to the appropriate lines of the data bus 20 through buffers (not
shown) and have their clocking inputs tried to a signal referred to as
PWRCTLWR*. The PWRCTLWR* signal is a signal which indicates that a write
operation has been directed to the power control register 109 and is of a
phase such that the rising edge of the signal is available when the data
is valid at the inputs to the various flip-flops. The non-inverted outputs
of the power control register flip-flops are combined to form the PWRCTL
data lines and are connected to the system address and data bus 20 via
appropriate buffering devices (not shown).
When the computer system C is in standby mode, which may be referred to as
being asleep, and the operator presses the standby switch 58, a one CLK
signal length pulse is developed at the output of the NAND gate 106 when
the standby switch 58 is released and is applied to the reset input of the
sleep flip-flop 110. This pulse resets the noninverting output of the
sleep flip-flop 110. The noninverting output of the sleep flip-flop 110 is
connected to one input of a two input NAND gate 118. The other input of
NAND gate 118 is connected to the inverted output of the LCD flip-flop
160. This dual connection of the sleep flip-flop output 110 and the LCD
flip-flop 116 output is used in the preferred embodiment because of
constraints relating to the powering sequence of the LCD 50. Therefore
when the output of the sleep flip-flop 110 goes low, the output of NAND
gate 118 goes high and therefore the signal present at the D input of a
D-type flip-flop 120 goes high. This flip-flop 120 is clocked by the
inverted CLK signal as produced by an inverter 122. When the next falling
edge of the CLK signal is encountered, the SLEEP* signal, which is the
non-inverted output of flip-flop 120, goes high indicating that the
computer system C is no longer in standby mode. The SLEEP* signal feeds
back to NOR gate 102 to clear the pulse provided by NAND gate 106.
The inverting output of flip-flop 120 is connected to the D input of a
D-type flip-flop 124. The clocking input to flip-flop 124 is provided by
the CLK signal, so at the next rising edge of the CLK signal the
noninverting output of flip-flop 124 goes low. This output of the
flip-flop 124 is tied to one input of a two input OR gate 126, with the
other input of the OR gate 126 being the CLK signal. Thus, when the
noninverting output of flip-fop 124 is low, the output of the OR gate 126
proceeds to follow the CLK signal and is referred to as the BCLK signal.
This is the blocked clock or stopped cock signal for use with the power
control logic circuitry 42 so that when the computer system C is in
standby mode even the portions of the power control circuitry 42 which can
be stopped are stopped.
When the computer system C is to enter standby mode, the inverting output
of the LCD flip-flop 116 is in a high state because in the preferred
embodiment it is desired that the LCD power be turned off prior to
removing the clock from the various portions of the computer system C. The
noninverting output of the sleep flip-flop 110 is set high on a following
access of the CPU 22 to the power control register 109, so that both
inputs of the two input NAND gate 118 are high so that a low signal is
presented to the input of flip-flop 120. At the next falling edge of the
CLK signal the SLEEP* signal goes low, indicating that the computer system
C is in the standby mode and the inverting output of flip-flop 120 goes
high, which output is then clocked through flip-flop 124 to stop operation
of the clock to the other portions of the power control logic circuitry 42
by means of OR gate 126.
The non-inverted output of the RAMDAC flip-flop 113 is supplied to one
input of an OR gate 128. The second input to OR gate 128 is the ACPWR
signal, which indicates that AC power is applied. The output of the OR
gate 128 is a RAMDACON signal to indicate the power should be turned on to
the RAMDAC located in the display control adaptor 38. As discussed, the
RAMDAC is useful only with an external monitor in the preferred embodiment
because the LCD display is not color and therefore there is no need to
perform the necessary color pallette lookups performed by the RAMDAC.
Therefore if the RAMDAC bit is set on or the computer system C is being
powered by the external AC supply, the RAMDAC is turned on. Otherwise the
RAMDAC is turned off to conserve power.
The non-inverting output of the modem flip-flop 112 is supplied to the D
input of a D-type flip-flop 130. The clocking signal to this flip-flop is
a signal referred to as CLK13.mu.S which provides an approximate 13
microsecond clocking signal to flip-flop 130. The output of flip-flop 130
is the MODEMON signal and is supplied to the D input of a second D-type
flip-flop 132 and to one input of a two input EQUAL gate 134. The MODEMON
signal is supplied to an FET 66 to control the power to modem 30. The
second flip-flop 132 is also clocked by the CLK13.mu.S signal and has its
non-inverting output connected to the second input of the EQUAL gate 134.
The output of the EQUAL gate 134 is supplied to one input of a two input
NAND gate 136. The output of NAND gate 136 is referred to as the MODEMRST
signal, the modem reset signal. The second input of the NAND gate 136 is
connected to the RESET* signal, which is the main reset signal present in
the computer system C. Assuming that the RESET* signal is high, the
MODEMRST signal is pulsed high for one 13 microsecond CLK signal cycle
when the modem flip-flop 112 output changes. Thus, there is a reset pulse
after the modem 30 is turned on to allow the modem 30 to properly
initialize itself.
The non-inverting output of the hard disk flip-flop 114 is the HDISKON
signal and is connected to an FET 68 to control the power to the hard disk
unit 48.
The non-inverting output of the sleep flip-flop 110 and the inverting
output of the LCD flip-flop 116 are provided to the two inputs of a NOR
gate 138. The output of the NOR gate 138 is the LCDON signal which is
connected to an FET 70 to control the supply of power to the LCD 50. The
coupling of the SLEEP and LCD flip-flop output signals is to prevent the
LCD power from being removed in improper sequence and possibly damaging
the LCD 50.
The computer system C includes a parallel printer interface 36. In the
preferred embodiment, this parallel printer interface 36 can be addressed
at any one of three selectable addresses which are generally referred to
as LPT1, LPT2 and LPT3. The selection of which of the three printer
locations is defined by the state of two bits in a peripheral control
register, the two signals corresponding to the two bits referred to as
PCR<6> and PCR<5>. These two signals are provided to the gating inputs of
a 4:1 multiplexer 150, which has an inverted output (FIG. 4). A signal
referred to as the LPT1* signal is applied to the zero channel input of
the multiplexer 150 and is true when an access is being made to the
address of the LPT1 printer which, in the preferred embodiment, has an
address of 3BC-3BF. A signal referred to as LPT2*, which is indicative of
an access to port address 37A-37F, is connected to the second input of the
multiplexer 150. A signal referred to as LPT3*, which goes low when an
access is made to the address 278-27F, is connected to the third input to
the multiplexer 150. The fourth input to the multiplexer 150 is tied to a
positive level. The output of the multiplexer 150 is a signal referred to
as PTR, and goes high to indicate that an access is being made to the
selected printer location. The PTR signal 150 is connected to one input of
a four input OR gate 152. Another of the inputs to this four input OR gate
152 is the output of yet another four input OR gate 154. The four inputs
to four input OR gate 154 are the HDlSK signal, the MODEM signal, the UART
signal, and the KEYBD signal. These signals represent, respectively,
accesses to the addresses of 1F0-1F7, 2F8-2FF, 3F8-3FF, and 060 and 064.
When any one of these signals is present, this indicates that the CPU 22
or other device controlling the bus may be accessing one of these
specified addresses.
A signal designated FLOPPY is supplied to one input of a series of three
NOR gates 156, 158 and 160. The FLOPPY signal indicates an access request
in the address range 3F0-3F7, which the complete range for access to the
floppy disk controller 32 in the preferred embodiment. However, because of
certain features in other control sequences which are present in the
computer system C that had to be retained for compatibility reasons, one
address in the range cannot be utilized for inactivity montoring because
this address is accessed on a relatively frequent basis to prevent other
potential systems problems from occurring and does not necessarily
indicate system activity. Therefore the FLOPPY signal must be combined
with other bits of the address to determine that the specific undesired
address is not being presented. The FLOPPY signal is first combined with
the zero or least significant address signal by NOR gate 160 so that any
access to an odd address produces a high level signal which is applied to
one input of the OR gate 152. The ADD<2> signal representing the second
east significant bit of the address is supplied to the an input of a NOR
gate 158 along with the FLOPPY signal, so that all addresses having a
least significant hexadecimal digit in the range 4-7 are selected. The
output from NOR gate 158 is supplied to one input of a two input OR gate
162, whose output is connected to the fourth input of the four input OR
gate 152. The second input to the OR gate 162 is provided from a third NOR
gate 156 whose inputs are the ADD<1> signal or next least significant bit
of the address and the FLOPPY signal, so that the output of the NOR gate
156 goes high only when an address having a least significant hexadecimal
digit of 0, 1, 4 or 5 is present. Thus, the NOR gates 156, 158 and 160
produce a high level signal for addresses in the range of 3F0-3F7, except
when the address is 3F2, which is the address accessed by the above-given
problem.
The output of the four input OR gate 152 indicates that a proper address of
the monitored devices has been presented on the address bus 20. This
signal is provided to one input of each of two different two input NAND
gates 164 and 166. The second input of the NAND gate 164 is a signal
referred to as I/ORD, which indicates that a valid I/O address space or
port read operation is in progress. The second input to the other NAND
gate 166 is a signal referred to as the I/OWR signal, which indicates that
a valid I/O address space write operation is in progress. The use of these
two signals is necessary in combination with the addressing information to
determine that the monitored devices are actually being accessed. The
outputs of the NAND gates 164 and 166 are supplied to two inputs of an AND
gate 168 whose output is the DEVACT* signal, which is low when a monitored
device is being accessed. The DEVACT* signal is low only the length of the
I/ORD or I/OWR signals in the preferred embodiment because the I/O control
signals are present for shorter periods than the address information.
The DEVACT* signal is applied to one input of a two input NAND gate 200
(FIG. 3). The second input to the NAND gate 200 is a signal designated
ACTMONWR*, which indicates that a write operation is occurring to the
activity monitor interval register. The ACTMONWR* signal is also supplied
to the enabling input of a latch 202. The data input signals to the latch
202 are provided by connection to the data bus 20, so that the latch 202
is a first register or buffer contained in the activity monitor timer T.
The output of the NAND gate 200 is connected to the clock input of a D-type
flip-flop 204. The D input is connected to a high level signal so that
whenever the DEVACT* signal is deactivated to a high state indicating that
an access to a monitored device has just completed, the flip-flop 204 is
clocked. The noninverted output of the flip-flop 204 is connected to the D
input of a second D-type flip-flop 206. The clocking input of the
flip-flop 206 is supplied by the BCLK signal. The inverting output of the
flip-flop 206 is connected to one input of a two input AND gate 208, whose
output is connected to the inverted chip enable input of a second latch
210. This use of two latches 202 and 210 allows the activity monitor timer
T to be double buffered. Additionally, the register 210 includes an output
which indicates that the value latched in the latch 210 is not zero. The
clocking input signal to the second latch 210 is the BCLK signal.
The output of AND gate 208 is also connected to one input of a two input OR
gate 212, whose other input is the BCLK signal. The output of OR gate 212
is fed back to the reset input of flip-flop 204 so that each time the
DEVACT* signal is propagated through the two flip-flops 204 and 206, the
first flip-flop 204 is cleared.
The inverting output of the second flip-flop 206 is also connected to one
input of a two input NAND gate 214. The output of the NAND gate 214 is
connected to the D input of a D-type flip-flop 216 whose clocking input is
supplied by the BCLK signal. The inverting output of the flip-flop 216 is
connected to one input of an AND gate 218 and the output of the AND gate
218 is connected to the inverted load input of the countdown timer 220,
which forms the loadable portion of the timing elements of the activity
monitor timer T. The timer 220 has an output which indicates when the
timer 200 has reached a zero value. The output of the AND gate 218 is also
connected to one input of a four input NAND gate 222 whose output is
designated the ACTIVE* signal and indicates that a device has been active
and the activity monitor timer T has not counted to zero. The NOTZERO
signal provided by the latch 210 is connected to one input of the NAND
gate 222 and the ZERO signal output from the timer counter 220 is provided
to yet another input of the NAND gate 222. The fourth and final input of
the NAND gate 222 is a signal described as IRQ15CLR, which indicates that
the interrupt request 15 has been cleared. The inputs to the NAND gate 222
are true only when the activity monitor timer T is enabled by the value of
the latch 210 not being zero, a device is not active as indicated by the
output of AND gate 218, the countdown timer 220 is at zero count and the
level 15 interrupt has been cleared. This is a general condition that the
computer system C has been inactive for a sufficient period of time as
indicated by the value from which the activity monitor timer T counted
down.
The IRQ15CLR signal and the NOTZERO signal are provided as two inputs to a
three input AND gate 224. The third input to AND gate 224 is a signal
referred to as 5SEC which is a pulse having a width of one BCLK signal
cycle and occurs every five seconds. This pulse is produced by a ripple
counter 226 which has the BCLK signal as one input to produce the
necessary pulse width, a second signal input of the CLK13.mu.S signal to
produce an initial clock cycle which is divided down to a five second
cycle and a reset signal provided by the output of the AND gate 218. The
output of the AND gate 224 is provided to the enable input of the
countdown timer 220 and is synchronized to the BCLK signal the clocking
input to the countdown time 220, so that the countdown timer 220 is
advanced or decremented only one count per five second interval. The data
outputs of the first latch 202 are connected in parallel to the data
inputs to the second latch 210, whose data outputs in turn are connected
to the inverting data inputs of the countdown timer 220. The inverted data
outputs of the timer 220 are provided to the data bus 20 over a line or
series of lines referred as to as the ACTMN data lines to provide the
activity monitor timer value to the CPU 22. In this way the CPU 22 can
determine the actual countdown time remaining prior to entering a sleep or
standby status.
The ACTIVE* signal is connected to the second input of NAND gate 214 and
when the ACTIVE* signal goes low, this causes the output of NAND gate 214
to go high, so that on the second BCLK signal rising edge after a
monitored device has been accessed, the countdown timer 220 is reloaded
and the process is reinitiated and the ACTIVE* signal returns to a high
state. This pulse width of the ACTIVE* signal is sufficient for the level
15 interrupt to be generated as needed to start execution of the interrupt
routine which determines if and when it is appropriate to go into standby
mode. The two latches 202 and 210 and the two flip-flops 206 and 216 are
reset by a low level of the RESET* signal.
Thus, the combination of flip-flops 204, 206 and 216 and various logic
gates 200, 208, 212, 214 and 218 reset and retrigger the countdown timer
220 each time a monitored device is activated. For example, a clocking
signal appears at flip-flop 204, which then provides a high signal to the
D input of flip-flop 206, whose inverting output in turn goes low at the
next rising edge of the BCLK signal. This low output on the inverting
output of flip-flop 206 enables the second latch 210 to be reloaded on the
next rising edge of the BCLK signal and the output of flip-flop 216 to go
low on that same BCLK signal edge. On the next BCLK signal rising edge
after that, the countdown timer 220 is reloaded and thus the countdown
process recommences.
The ACTIVE* signal is applied to one input of a two input NAND gate 250
(FIG. 5). The output of this NAND gate 250 is connected to the D input of
a D-type flip-flop 252. This flip-flop 252 is clocked by the BCLK signal.
The non-inverting output of flip-flop 252 is the active status bit of the
interrupt request register and is provided to the processor by means of
the IRQDATA<7-0> lines and appropriate buffering. The non-inverting output
of flip-flop 252 is also supplied to the D input of a flip-fop 254, which
flip-flop 254 is also clocked by the BCLK signal. The inverting output of
the first flip-flop 252 is connected to the second input of the NAND gate
250 and to the first input of a NOR gate 256. By this connection, the D
input to the flip-flop 252 remains high after the initial pulse is
received on the ACTIVE* signal so that the state of the activity status of
the computer system C can be determined at any time. The output of the
second flip-flop 254 is provided to the second input of the NOR gate 256,
whose output is connected to one input of a six input NOR gate 258. The
output of the two input NOR gate 256 is a pulse having a length of one
BCLK signal cycle. In this manner only a short pulse is formed and
provided to the NOR gate 258 when the inactivity timeout is reached to
cause the IRQ15REQ signal to be developed.
As can be seen by the fact that there are six inputs to the NOR gate 258,
there are a plurality of different ways in which the IRQ15REQ signal can
be generated. These additional ways are provided in the preferred
embodiment to allow the computer system C to know the states of various
events and switches relating to power usage and to warn the user at
appropriate intervals. For example, the ACPWR* signal is provided to the D
input D-type of flip-flop 260, whose clocking signal is the BCLK signal.
The non-inverting output of the flip-flop 260 is connected to the D input
of a D-type flip-flop 262 and to one input of a two input XOR gate 264.
The second input to the XOR gate 264 is provided by the noninverting
output of the second flip-flop 262, which flip-flop is clocked by the BCLK
signal. The output of the XOR gate 264 is thus a one BCLK signal cycle
length pulse which occur whenever the condition of the AC power changes
and is provided to the NOR gate 258 to generate the IRQ15REQ signal. The
state of the ACPWR* signal is stored and transmitted to the IRQDATA lines
by the inverting output of the flip-flop 260. Thus, the NOR gate 258 is
utilized to allow the computer system C to note any change in the AC power
status such as, for example, when the AC adaptor is provided or removed.
This allows the computer system C to note when it is entering
battery-powered operation and thus the power conservation mode may be
appropriate. This operation is seen in more detail in the flowchart
illustrations of the operating sequences of the computer system C.
Similar flip-flop circuits are present for utilizing the LOWBAT1 and
LOWBAT2 signals. Thus two inputs to the NOR gale 258 indicate whenever the
computer system C has changed the battery charge status to or from LOWBAT1
or LOWBAT2. The actual LOWBAT signals are latched by a first D-type
flip-flop 290 and 292 in the series and the noninverted outputs are
presented to the IRQDATA lines. A second D-type flip-flop 294 and 296 is
closed by the BCLK signal and has the D input connected to the preceding
flip-flop 290 and 292 noninverting output. The noninverting outputs of the
flip-flops 290 and 292 and 294 and 296 are the inputs to an XOR gate 297
and 298, whose output is connected to NOR gate 258 to produce the
necessary signal to trigger a level 15 interrupt | | |
