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Claims  |
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What is claimed is:
1. A semiconductor memory device having a memory cell array comprising a
plurality of memory cells arranged in rows and columns, a plurality of
word lines for selecting one row out of said memory cell array, and a
plurality of bit lines for selecting one column out of said memory cell
array, said plurality of bit lines constituting a pair of folded bit
lines, comprising:
row address inputting means for receiving an externally applied row
address,
row selecting means responsive to the row address from said row address
inputting means for selecting one row out of said memory cell array,
column address inputting means for receiving an externally applied column
address,
column selecting means responsive to the column address from said column
address inputting means for selecting one bit line pair to select memory
cells in one column out of said memory cell array,
write-in signal inputting means for receiving an externally applied
write-in signal,
a pair of write-in data transferring lines for transferring data to be
written in a memory cell selected by said row address and said column
address at the time of data writing,
combining means for combining an output of said column selecting means and
said write-in signal from said write-in signal inputting means to form an
input line connect signal,
connecting means responsive to said input line connect signal for
connecting the bit line pair selected by said column address to said pair
of write-in data transferring lines at the time of data writing,
a pair of read-out data transferring lines provided separately from said
pair of write-in data transferring lines for transferring data on a bit
line pair selected by said column address at the time of data reading, and
amplifying means responsive to the output of said column selecting means
for driving said pair of read-out data transferring lines in accordance
with data on said selected bit line pair,
said amplifying means comprising
means for detecting a voltage difference of said selected bit line pair,
first and second voltage amplifying means for respectively amplifying
voltages on bit lines of said selected bit line pair,
means for establishing a positive feedback signal flow path between said
first and second voltage amplifying means, to increase the rate of the
change in voltage of said first and second voltage amplifying means,
means responsive to said first and second voltage amplifying means for
adjusting first and second currents,
means for converting said first and second currents into a voltage
difference, and
means for applying said voltage difference to said pair of read-out data
transferring lines.
2. The semiconductor memory device according to claim 1, wherein said
connecting means comprises
a plurality of switching means each connected between each of said
plurality of bit line pairs and said pair of write-in data transferring
lines and responsive to the output of said column selecting means and said
write-in signal from said write-in signal inputting means to be rendered
conductive.
3. The semiconductor memory device according to claim 2, which further
comprises PG,69
writing column selecting means responsive to said write-in signal from said
write-in signal inputting means for outputting the output of said column
selecting means as a column selection signal for writing.
4. The semiconductor memory device according to claim 3, wherein each of
said plurality of switching means comprises
a field effect transistor connected between one of the corresponding bit
line pair and one of said pair of write-in data transferring lines and
having a gate receiving said column selecting signal for writing, and
a field effect transistor connected between the other of said corresponding
bit line pair and the other of said pair of write-in data transferring
lines and having a gate receiving said column selecting signal for
writing.
5. The semiconductor memory device according to claim 1, wherein said
amplifying means comprises a current-mirror type amplifier comprising a
plurality of insulating gate type first, second, third and fourth field
effect devices provided corresponding to said plurality of bit lines
pairs, a plurality of first and second nodes provided corresponding to
said plurality of bit lines pairs, and at least one insulating gate type
fifth and sixth field effect devices,
each of said plurality of first field effect devices being coupled between
a predetermined first potential and the corresponding first node and
having a control terminal connected to one of the corresponding bit line
pair,
each of said plurality of second field devices being coupled between the
corresponding second node and having a control terminal connected to the
other of the corresponding bit line pair,
each of said plurality of third field effect devices being coupled between
the corresponding first node and one of said pair of read-out data
transferring lines and having a control terminal receiving the output of
said column selecting means,
each of said plurality of fourth field effect devices being coupled between
the corresponding second node and the other of said pair of read-out data
transferring lines and receiving the output of said column selecting
means,
said fifth field effect device being coupled between a predetermined second
potential and one of said pair of read-out data transferring lines and
having a control terminal, and
said sixth field effect device being coupled between said predetermined
second potential and the other of said pair of read-out data transferring
lines and having a control terminal connected to the control terminal of
said fifth field effect device and one or the other of said pair of
read-out data transferring lines.
6. The semiconductor memory device according to claim 1, which further
comprises read-out signal inputting means for receiving an externally
applied read-out signal,
said amplifying means being responsive to the output of said column
selecting means and said read-out signal from said read-out signal
inputting means to be activated.
7. The semiconductor memory device according to claim 6, which further
comprises reading column selecting means responsive to said read-out
signal (R) from said read-out signal inputting means for outputting the
output of said column selecting means as a column selecting signal for
reading.
8. A semiconductor memory device having a memory cell array comprising a
plurality of memory cells arranged in rows and columns, a plurality of
word lines for selecting one row out of said memory cell array, and a
plurality of bit lines for selecting one column out of said memory cell
array, said plurality of bit lines constituting a pair of folded bit
lines, comprising:
row address inputting means for receiving an externally applied row
address,
row selecting means responsive to the row address from said row address
inputting means for selecting one row out of said memory cell array,
column address inputting means receiving an externally applied column
address,
column selecting means responsive to the column address from said column
address inputting means for selecting one bit line pair to select one
column out of said memory cell array,
a pair of write-in data transferring lines connected to the bit line pair
selected by said column address in response to an output of said column
selecting means to transfer data to be written in a memory cell selected
by said row address and said column address, at the time of data writing,
a pair of read-out data transferring lines provided separately from said
pair of write-in data transferring lines for transferring data on a bit
lint pair selected by said column address at the time of data reading, and
amplifying means responsive to the output of said column selecting means
for driving said pair of read-out data transferring lines in accordance
with data on said selected bit line pair,
said amplifying means comprising a plurality of insulating gate type first,
second, third and fourth field effect devices provided corresponding to
the plurality of bit line pairs, a plurality of first and second nodes
provided corresponding to said plurality of bit line pairs and at least
one of insulating gate type fifth and sixth field effect devices,
each of said plurality of first field effect devices being coupled between
a predetermined first potential and the corresponding first node and
having a control terminal connected to one bit line of the corresponding
bit line pair,
each of said plurality of second field effect devices being coupled between
said predetermined first potential and the corresponding second node and
having a control terminal connected to the other bit line of the
corresponding bit line pair,
each of said plurality of third field effect devices being coupled between
the corresponding first node and one of said pair of read-out data
transferring lines and having a control terminal receiving the output of
said column selecting means,
each of said plurality of fourth field effect devices being coupled between
the corresponding second node and the other of said pair of read-out data
transferring lines and having a control terminal receiving the output of
said column selecting means,
said fifth field effect device being coupled between a predetermined second
potential and one of said pair of read-out data transferring lines and
having a control terminal,
said sixth field effect device being coupled between said predetermined
second potential and the other of said pair of read-out data transferring
lines and having a control terminal connected to the control terminal of
said fifth field effect device and one or the other of said pair of
read-out data transferring lines.
9. A semiconductor memory device having a memory cell array comprising a
plurality of memory cells arranged in rows and columns, a plurality of
word lines for selecting one row out of said memory cell array, and a
plurality of bit lines for selecting one column out of said memory cell
array, said plurality of bit lines constituting a pair of folded bit
lines, comprising:
row address inputting means for receiving an externally applied row
address,
row selecting means responsive to the row address from said row address
inputting means for selecting one row out of said memory cell array,
column address inputting means receiving an externally applied column
address,
column selecting means responsive to the column address from said column
address inputting means for selecting one bit line pair to select the
memory cells in one column out of said memory cell array,
a pair of write-in data transferring lines, connected to the bit line pair
designated by said column address in response to an output of said column
selecting means to transfer data to be written in a memory cell selected
by said row address and said column address at the time of data writing,
a pair of read-out data transferring lines provided separately from said
pair of write-in data transferring lines for transferring data on the bit
line pair designated by said column address at the time of data reading,
and
a plurality of stages of amplifying means responsive to the output of said
column selecting means to be rendered active,
the first stage of amplifying means out of said plurality of stages of
amplifying means amplifying data on the bit line pair designated by said
column address, and the last stage of amplifying means out of said
plurality of stages of amplifying means amplifying an output of the
preceding stage of amplifying means to provide the amplified output to
said pair of read-out data transferring lines,
each of said plurality of stages of amplifying means comprising
means for detecting a voltage difference of said selected bit line pair
first and second voltage amplifying means for respectively amplifying
voltages on bit lines of said selected bit line pair,
means for establishing a positive feedback signal flow path between said
first and second voltage amplifying means, to increase the rate of the
change in voltage of said first and second voltage amplifying means,
means responsive to said first and second voltage amplifying means for
adjusting first and second currents,
means for converting said first and second currents to a voltage
difference, and
outputting means for outputting said voltage difference.
10. The semiconductor memory device according to claim 9, wherein each of
said plurality of stages of amplifying means comprises a current-mirror
type sense amplifier comprising a plurality of insulating gate type field
effect transistors.
11. An accessing method in a semiconductor memory device comprising a
plurality of word lines; a plurality of bit lines having a folded bit line
structure in which two bit lines are paired with each other; a plurality
of memory cells respectively provided at intersections of the word lines
and the bit lines; a first pair of data buses for transferring data to be
written; a second pair of data buses provided separately from said first
pair of data buses for transferring data to be read; and amplifying means
provided between said second pair of data buses and said plurality of bit
line pairs, which comprises the steps of:
selecting any one of said plurality of word lines in response to an
externally applied row address to activate the selected word line,
combining an externally applied column address and an externally applied
write-in signal to form an input line connect signal,
connecting, in response to said input line connect signal, one bit line
pair selected by said column address to said first pair of data buses at
the time of data writing,
combining the externally applied column address and an externally applied
read-out signal to form an output line connect signal, and
activating, in response to the output line connect signal, said amplifying
means to drive said first pair of data buses in accordance with data on
one bit line pair designated by said column address at the time of data
reading.
12. A semiconductor memory device comprising:
a plurality of memory cells in rows and columns, a plurality of word lines
arranged in rows, each word line connected to said memory cells arranged
in a corresponding row, respectively,
a plurality of bit line pairs arranged in columns, each bit line pairs
having a folded bit line structure and connected to said memory cells
arranged in a corresponding column, respectively,
a pair of input lines, one of a pair of input lines connected to one of
said bit line pairs through a first transfer means for writing data, the
other of a pair of input lines connected to the other of said bit line
pairs through a second transfer means,
a pair of output lines connected to a first potential node, and
a plurality of transfer means for reading out data, each transfer means for
reading out data arranged in columns and having a first, second, third and
fourth transistors having a pair of main electrode and control electrode,
one of a pair of main electrodes of said first transistor connected to a
second potential node, the control electrode of said first transistor
connected to one of a corresponding bit line pairs, said second transistor
connected between the other of a pair of main electrodes of said first
transistor and one of a pair of said output lines, the control electrode
of said second transistor receiving a column address signals, one of a
pair of main electrodes of said third transistor connected to said second
potential node, the control electrode of said third transistor connected
to the other of a corresponding bit line pairs, said fourth transistor
connected between the other of a pair of main electrode of said third
transistor and the other of a pair of said output lines, the control
electrode of said fourth transistor receiving said column address signals.
13. A semiconductor memory device comprising;
a plurality of memory cells arranged in rows and columns,
a plurality of word lines arranged in rows, each word line connected to
said memory cells arranged in a corresponding row, respectively,
a plurality of bit line pairs arranged in columns, each bit line pairs
having a folded bit line structure and connected to said memory cells
arranged in a corresponding column, respectively,
a pair of output lines, one of a pair of output lines connected to one of
said bit line pairs through a first transfer means for reading out data,
the other of a pair of output lines connected to the other of said bit
line pairs through a second transfer means for reading out data,
a pair of input lines, and
a plurality of transfer means for writing data, each transfer means for
writing data arranged in columns and having first and second transistors,
said first transistor connected between one of a pair of input lines and
one of a corresponding bit line pairs, said second transistor connected
between the other of a pair of input lines and the other of said
corresponding bit line pairs, the control electrode of said first and
second transistors receiving a combined write-in and column address
signal.
14. A connection means for use in a dynamic random access memory for
connection of pairs of bit lines to respective output lines comprising:
addressable means for outputting an enabling signal on an output enabling
line in response to an address applied thereto,
two current mirror amplifiers each amplifier comprising a pair of
transistors comprising a first and a second field effect transistor having
the conduction terminals thereof connected in series between a power
supply voltage source and a reference voltage source, the gates of the
first field effect transistors in each amplifier having control terminals
connected together and to one of said output lines and the control
terminals of each of said second field effect transistors being connected
to respective ones of said pair of bit lines, said output lines being
connected to a conduction terminal of said first field effect transistor,
and
a pair of further transistors, the conduction terminals of each of said
further transistors being connected in series with the first and second
transistors of a respective current mirror amplifier and having a control
terminal thereof being connected to said output enabling line.
15. A connection means as recited in claim 14 wherein each of said pair of
further transistors is interposed between the first and second field
effect transistors of each said current mirror amplifier.
16. A connection means for use in a dynamic random access memory for
connection of pairs of intermediate output lines to respective data output
lines comprising:
activation means for producing a selective activation signal on an
activation line,
two current mirror amplifiers each amplifier comprising a pair of
transistors comprising a pair of first field effect transistors and a pair
of second field effect transistor having the conduction terminals thereof
connected in series between a power supply voltage source and a common
node, the gates of the first field effect transistors in each pair having
control terminals connected together and to one of said conduction
terminals one field effect transistor of each pair of said first field
effect transistors and the control terminals of each of said second field
effect transistors being connected to respective ones of said intermediate
output bit lines, said data output lines being connected to a conduction
terminal of the other first field effect transistor of each pair, and
a pair of further transistors of opposite conductivity types, the
conduction terminals of one transistor of said pair being connected in
series between said common node and a source of reference voltage and the
conduction terminals of the other transistor of said pair being connected
between said data output lines for equalization of the potentials thereon
and having control terminals of both said further transistors being
connected to said activation line.
17. A connection means as recited in claim 16, further including a further
current mirror amplifier comprising two further pairs of further first
field effect transistors and further second field effect transistors, said
further first and further second field effect transistors having
conduction terminals thereof connected in series between a power supply
voltage source and a further common node, the bases of the said further
first field effect transistors in each pair having control terminals
connected together and to one of said conduction terminals of one field
effect transistor of each pair of said further first field effect
transistors and the control terminals of each of said second field effect
transistors being connected to respective ones of said pair of data output
lines, outputs of said further current mirror amplifier being taken at the
connection of the conduction terminals of each pair of said further first
and said further second field effect transistors, and
another transistor having conduction terminals connected to said further
common node and a reference voltage source and a control terminal thereof
connected to said activation line.
18. A semiconductor memory device having a memory cell array comprising a
plurality of memory cells arranged in rows and columns, a plurality of
word lines for selecting one row out of said memory cell array, and a
plurality of bit lines for selecting one column out of said memory cell
array, said plurality of bit lines constituting a pair of folded bit
lines, comprising:
row address inputting means for receiving an externally applied row
address,
row selecting means responsive to the row address from said row address
inputting means for selecting one row out of said memory cell array,
column address inputting means for receiving an externally applied column
address,
column selecting means responsive to the column address from said column
address inputting means for selecting one bit line pair to select memory
cells in one column out of said memory cell array,
write-in signal inputting means for receiving an externally applied
write-in signal,
a pair of write-in data transferring lines for transferring data to be
written in a memory cell selected by said row address and said column
address at the time of data writing,
combining means for combining an output of said column selecting means and
said write-in signal from said write-in signal inputting means to form an
input line connect signal;
connecting means responsive to said input line connect signal for
connecting the bit line pair selected by said column address to said pair
of write-in data transferring lines at the time of data writing,
a pair of read-out data transferring lines provided separately from said
pair of write-in data transferring lines for transferring data on a bit
line pair selected by said column address at the time of data reading, and
amplifying means including a current mirror responsive to the output of
said column selecting means for driving said pair of read-out data
transferring lines in accordance with data on said selected bit line pair.
19. The semiconductor memory device according to claim 18, wherein said
current mirror comprises MOS type transistors.
20. The semiconductor memory device according to claim 18, wherein said
connecting means comprises a plurality of switching means each connected
between each of said plurality of bit line pairs and said pair of write-in
data transferring lines and responsive to the output of said column
selecting means and said write-in signal from said write-in signal
inputting means to be rendered conductive.
21. The semiconductor memory device according to claim 20, further
comprising writing column selecting means responsive to said write-in
signal from said write-in signal inputting means for outputting the output
of said column selecting means as a column selection signal for writing.
22. The semiconductor memory device according to claim 21, wherein each of
said plurality of switching means comprises:
a field effect transistor connected between one of the corresponding bit
line pair and one of said pair of write-in data transferring lines and
having a gate receiving said column selecting signal for writing, and
a field effect transistor connected between the other of said corresponding
bit line pair and the other of said pair of write-in data transferring
line and having a gate receiving said column selecting signal for writing.
23. The semiconductor memory device according to claim 18, further
comprising read-out signal inputting means for receiving an externally
applied read-out signal, wherein said amplifying means is responsive to
the output of said column selecting means and said read-out signal from
said read-out signal inputting means to be activated.
24. The semiconductor memory device according to claim 23, further
comprising reading column selecting means responsive to said read-out
signal from said read-out signal inputting means for outputting the output
of said column selecting means as a column selecting signal for reading.
25. A semiconductor memory device having a memory cell array comprising a
plurality of memory cells arranged in rows and columns, a plurality of
word lines for selecting one row out of said memory cell array, and a
plurality of bit lines for selecting one column out of said memory cell
array, said plurality of bit lines constituting a pair of folded bit
lines, comprising:
row address inputting means for receiving an externally applied row
address,
row selecting means responsive to the row address from said row address
inputting means for selecting one row out of said memory cell array,
column address inputting means for receiving an externally applied column
address,
column selecting means responsive to the column address from said column
address inputting means for selecting one bit line pair to select memory
cells in one column out of said memory cell array,
write-in signal inputting means for receiving an externally applied
write-in signal,
a pair of write-in data transferring lines for transferring data to be
written in a memory cell selected by said row address and said column
address at the time of data writing,
combining means for combining an output of said column selecting means and
said write-in signal from said write-in signal inputting means to form an
input line connect signal;
connecting means responsive to said input line connect signal for
connecting the bit line pair selected by said column address to said pair
of write-in data transferring lines at the time of data writing,
a pair of read-out data transferring lines provided separately from said
pair of write-in data transferring lines for transferring data on a bit
line pair selected by said column address at the time of data reading, and
amplifying means including a current mirror responsive to the output of
said column selecting means for driving said pair of read-out data
transferring lines in accordance with data on said selected bit line pair.
26. The semiconductor memory device according to claim 25, wherein said
current mirror comprises MOS type transistors.
27. The semiconductor memory device according to claim 25, wherein said
connecting means comprises a plurality of switching means each connected
between each of said plurality of bit line pairs and said pair of write-in
data transferring lines and responsive to the output of said column
selecting means and said write-in signal from said write-in signal
inputting means to be rendered conductive.
28. The semiconductor memory device according to claim 27, further
comprising writing column selecting means responsive to said write-in
signal from said write-in signal inputting means for outputting in the
output of said column selecting means as a column selection signal for
writing.
29. The semiconductor memory device according to claim 28, wherein each of
said plurality of switching means comprises:
a field effect transistor connected between one of the corresponding bit
line pair and one of said pair of write-in data transferring lines and
having a gate receiving said column selecting signal for writing, and
a field effect transistor connected between the other of said corresponding
bit line pair and the other of said pair of write-in data transferring
line and having a gate receiving said column selecting signal for writing.
30. The semiconductor memory device according to claim 25, further
comprising read-out signal inputting means for receiving an externally
applied read-out signal, wherein said amplifying means is responsive to
the output of said column selecting means and said read-out signal from
said read-out signal inputting means to be activated.
31. The semiconductor memory device according to claim 30, further
comprising reading column selecting means responsive to said read-out
signal from said read-out signal inputting means for outputting the output
of said column selecting means as a column selecting signal for reading.
32. An accessing method in a semiconductor memory device comprising a
plurality of word lines; a plurality of bit lines having a folded bit line
structure in which two bit lines are paired with each other; a plurality
of memory cells respectively provided at intersections of the word lines
and the bit lines; a first pair of data buses for transferring data to be
written; a second pair of data buses provided separately from said first
pair of data buses for transferring data to be read; and amplifying means
provided between said second pair of data buses and said plurality of bit
line pairs, which comprises the steps of:
selecting any one of said plurality of word lines in response to an
externally applied row address to activate the selected word line,
combining an externally applied column address and an externally applied
write-in signal to form an input line connect signal, and
connecting, in response to said input line connect signal, one bit line
pair selected by said column address to said firs pair of data buses at
the time of data writing. |
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Claims |
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Description |
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CROSS-REFERENCE TO RELATED APPLICATIONS
The present application is related to the copending application Ser. No.
269,757, filed Nov. 8, 1988 commonly assigned with the present invention.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor memory devices
having separate read and write buses, and more particularly, to an
improved construction thereof and an operating method therefor, wherein
access time for reading out data from the device is reduced to provide a
high-speed operation.
2. Description of the Background Art
Recently, it has been desired in a highly integrated memory device such as
a dynamic MOSRAM (Random Access Memory using MOS transistors) to achieve
high integration density for increasing storage capacity thereof and to
increase the speed of a reading operation by substantially reducing access
time (time required for reading out data).
FIG. 1 is a diagram showing schematically an entire structure of a
conventional semiconductor memory device. This semiconductor memory device
is a dynamic random access memory (DRAM).
In FIG. 1, a memory cell array 101 comprises a plurality of memory cells
arranged in of rows and columns so as to have a folded bit line structure.
An address buffer 102 generates an internal row address signal and an
internal column address signal upon receipt of an externally applied
address signal ADD. A row decoder 103 is responsive to the internal row
address signal from the address buffer 102 for selecting the memory cells
in one row out of the memory cell array 101. The column decoder 104 is
responsive to the internal column address signal from the address buffer
102 for selecting the memory cells in one column (a single bit line pair)
out of the memory cell array 101. A block 105 (including a sense amplifier
portion and an I/O portion) amplifies a potential difference between
signals on the bit line pair, and connects the selected bit line pair to a
data input/output line in response to a column decoded signal from the
column decoder 104. A write-in buffer 106 receives externally applied
write data D.sub.IN for converting the received write data D.sub.IN into a
set of complementary data (D.sub.IN , D.sub.IN) to transfer the same to
the I/O portion in the block 105. A read-out buffer 107 receives the data
from the I/O portion in the block 105 for outputting the same to the
exterior as an output signal D.sub.OUT. A clock generator 108 generates
signals such as a row address strobe signal RAS and a column address
strobe signal CAS for providing timing of initiating a memory cycle and
timing of accepting an address signal.
The row address strobe signal RAS from the clock generator 108 is applied
to the address buffer 102, the row decoder 103 and the like, while the
column address strobe signal CAS is applied to the address buffer 102, the
column decoder 104 and the like.
As shown in FIG. 2, the row address strobe signal RAS provides timing of
accepting the row address signal in the address buffer 102, while the
column address strobe signal CAS provides timing of accepting the column
address signal in the address buffer 102. The row address signal and the
column address signal are applied to the address buffer 102 in a time
series. In addition, timing of decoding the address signal in the row
decoder 103 and timing of decoding the address signal in the column
decoder 104 are respectively provided by the row address strobe signal RAS
and the column address strobe signal CAS.
FIG. 3 is a diagram showing a structure of a main part of the memory cell
array shown in FIG. 1, showing specifically one example of a structure of
a block 150 represented by a dotted line.
In FIG. 3, a bit line pair BL and BL having a folded bit line structure is
typically shown. The bit lines BL and BL are paired with each other, to
constitute a folded bit line pair. More specifically, complementary
signals appear on the bit lines BL and BL. A plurality of word lines are
provided in a direction perpendicularly intersecting with the bit lines BL
and BL. In FIG. 3, only a single word line WL is typically shown. Memory
cells are respectively provided at intersections of the word line and the
bit lines, the memory cells being arranged in rows and columns. In FIG. 3,
only a single memory cell 1 provided at the intersection of the bit line
BL and the word line WL is typically shown. The memory cell 1 is of a
single transistor/a single capacitor type, which comprises a memory
capacitor CO for storing information and an N channel MIS (Metal Insulator
Semiconductor) transistor Q0.
In order to differentially amplify a potential difference between signals
on the bit line pair BL and BL, there are provided flip-flop type sense
amplifiers 2 and 3. The sense amplifier 2 comprises N channel MIS
transistors Q1 and Q2. The sense amplifier 2 is activated in response to a
signal from sense amplifier activating means 4, to discharge the bit line
on the lower potential side such that a potential thereon becomes a ground
potential. The sense amplifier activating means 4 comprises an N channel
MIS transistor Q5 which is turned on in response to a sense amplifier
activation signal SO to connect a node N1 to the ground potential. The
sense amplifier 3 comprises P channel MIS transistors Q3 and Q4. The sense
amplifier 3 is activated in response to a signal from sense amplifier
activating means 5, to charge the bit line on the higher potential side
such that a potential thereon becomes a power-supply potential Vcc. The
sense amplifier activating means 5 comprises a P channel MIS transistor Q6
which is turned on in response to a sense amplifier activation signal SO
to connect a node N2 to the power-supply potential Vcc.
Equalizing/precharging means 6 precharges each of the bit lines BL and BL
at a predetermined precharge potential V.sub.BL and equalizes the
potentials on the bit lines BL and BL before initiation of and after
termination of a memory cycle (i.e., at standby time). The precharge
potential V.sub.BL is generally generated by an internal voltage
generating circuit, which is set to a predetermined potential (for
example, one-half of the power-supply potential Vcc, i.e., Vcc/2).
Additionally, N channel MIS transistors Q10 and Q11 which are turned on in
response to a column decoded signal Y from the column decoder (see in FIG.
1) are connected between the bit line pair BL and BL and a data
input/output line pair I/O and I/O. The data input/output line pair I/O
and is generally precharged at a predetermined potential V'.sub.BL by N
channel MIS transistors Q22 and Q23 which are turned or in response to a
clock signal CLK. The data input/output line pair I/O and I/O exchanges
data through input/output buffers.
FIG. 4 is a signal waveform diagram showing a reading operation of the
conventional semiconductor memory device, the same signs as those shown in
FIG. 3 representing the change in potential in the corresponding portions.
Before the time T1, an equalizing signal EQ is at a high level, an
equalizing transistor Q7 and precharging transistors Q8 and Q9 are all in
the on state, the bit lines BL and BL being precharged at a predetermined
potential V.sub.BL.
At the time T1, when the equalizing signal EQ is lowered from a high level
to a low level, the transistors Q7, Q8, and Q9 are all turned off, so that
the bit lines BL and BL are rendered electrically floating. Consequently,
a precharging/equalizing operation is terminated. At the time T2, when a
single word line WL is selected in response to a row decoded signal from a
row decoder, a potential on the word line WL is changed from a low level
to a high level. Consequently, the transistor Q0 of the memory cell 1
connected to the word line WL is turned on, so that the memory capacitor
CO is connected to the bit line BL. As a result, the change in potential
corresponding to information stored in the memory cell 1 occurs on the bit
line BL. When the memory cell 1 stores information "1", the potential on
the bit line BL is raised only slightly, as compared with the precharge
potential as represented by solid lines in FIG. 4, while the bit line BL
is held at the precharge potential.
When a potential of a read-out signal on the bit line pair BL and BL
becomes stable, the sense amplifier activation signals SO and SO
respectively start to be raised and lowered, at the time T3. Consequently,
the transistors Q5 and Q6 are turned on, so that the nodes N1 and N2 are
respectively charged and discharged such that potentials thereof
respectively become the ground potential and the power-supply potential
Vcc. As a result, the flip-flop type sense amplifiers 2 and 3 are both
activated, so that the bit line BL on the higher potential side out of the
bit lines BL and BL is charged through the sense amplifier 3 such that the
potential thereon becomes the power-supply potential Vcc, while the bit
line BL on the lower potential side is discharged through the sense
amplifier 2 such that the potential thereon becomes the ground potential.
More specifically, a very small potential difference between the signals
on the bit line pair BL and BL is amplified.
After an amplifying operation of the sense amplifiers 2 and 3, when the
column decoded signal Y from the column decoder becomes a high level at
the time T4, the transistors Q10 and Q11 are turned on, so that the
potentials on the bit lines BL and BL are respectively transmitted to the
data input/output lines I/O and I/O. The potentials transmitted to the
data input/output lines I/O and are amplified by amplifying means such as
a preamplifier (not shown) and then, transmitted to the exterior through
data output buffers and external output terminals (not shown).
When the transfer of data to the external output terminals is terminated,
the potential on the word line WL is changed from a high level to a low
level at the time T5, and the column decoded signal Y is also changed from
a high level to a low level. Consequently, the potentials on the data
input/output line pair I/O and I/O are returned to the precharge
potential.
Then, at the time T6, the sense amplifier activation signals SO and SO are
respectively changed to a low level and a high level, so that the sense
amplifiers 2 and 3 are both rendered inactive. On this occasion, the
equalizing signal EQ also becomes a high level, so that the
precharging/equalizing means 6 is activated. As a result, the bit lines BL
and BL are precharged at a predetermined potential V.sub.BL and the
potentials on the bit lines BL and BL are equalized. The foregoing is the
outline of the data reading operation.
On the other hand, in the data writing operation, timing of a signal
waveform is the same as that shown in FIG. 4, in which data flows in a
direction opposite to that in the reading operation, i.e., in the
direction from a read-out buffer to a selected memory cell through a data
input/output line pair. More specifically, write-in data externally
applied through a write-in buffer (not shown) is transferred to the data
input/output line pair I/O and I/O in a complementary manner (for example,
D.sub.IN and D.sub.IN). After an operation sequence from the time T1 to
the time T3, when the column decoded signal Y is changed from a low level
to a high level at the time T4, the transistors Q10 and Q11 are turned on,
so that signal potentials on the data input/output lines I/O and I/O are
transmitted to the selected memory cell. In the above described manner,
writing is performed.
On this occasion, the sense amplifiers 2 and 3 are also activated at the
time T3, and the potential difference between the signals which appear on
the bit lines BL and BL by the change of the potential on the word line WL
to a high level. However, the write-in data is transferred to the data
input/output line pair I/O and I/O through the write-in buffer from the
exterior. Thus, even if the signal level amplified by the sense amplifiers
2 and 3 is opposite to the signal potential level of the write-in data,
the signal potential corresponding to the write-in data appears on the bit
line pair BL and BL. Consequently, the write-in data is written into the
selected memory cell through the transistor Q0 in the on state.
As described in the foregoing, in the construction of the conventional
semiconductor memory device, data is read out and written through the same
data input/output line pair I/O and I/O. Thus, even in reading out data,
the bit line pair BL and BL is connected to the data input/output line
pair I/O and I/O through the transistors Q10 and Q11. In order to read out
data at high speed, it is preferable to connect the bit line pair to the
data input/output line pair as fast as possible. However, in FIG. 4, when
the bit line pair and the data input/output line pair are connected to
each other in a period, for example, from the time T2 when the potential
on the word line WL rises to the time T3 when a sensing operation is
initiated by activation of the sense amplifiers 2 and 3, a load
capacitance of the data input/output line pair is applied to the bit
lines, so that the levels of the read-out signals on the bit lines are
lowered. Consequently, the sense amplifiers can not perform a reliable
sensing operation and a malfunction may occur. Thus, it is necessary to
connect the bit line pair to the data input/output line pair after the
sense amplifiers 2 and 3 are activated and the signal potentials on the
bit line pair BL and BL become stable. The connection between the selected
bit line pair and the data input/output line pair at the time of data
reading can not be made before the time T3.
Therefore, the conventional semiconductor memory device has the
disadvantage that | | |
