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Claims  |
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We claim:
1. A microcomputer comprising memory and a processor configured to execute
a plurality of concurrent processes by said processor in accordance with a
plurality of program steps, at least some of said processes being time
dependent, the microcomputer including a scheduling system comprising:
(i) an addressable storage element for indicating a process which is being
executed by said processor, said process being referred to as the current
process;
(ii) a timer list coupled to said storage element for identifying one or
more processes which form a time-ordered collection awaiting execution by
said processor after respective scheduling times for the processes in said
collection;
(iii) a set of storage locations associated with said timer list for
indicating scheduling times when the processes in said collection become
ready for execution;
(iv) a control system coupled to said timer list and to said processor to
cause said processor to add a further process to said collection at a
time-ordered position between a preceding process having an earlier
scheduling time and a following process having a later scheduling time;
(v) a next process indicator to indicate the next process in said
time-ordered collection for execution by said processor, including timing
logic responsive to said next process indicator to make said next process
the current process for execution after its scheduling time occurs.
(vi) a program stage indicator for each concurrent process; said processor
including timing logic responsive to said next process indicator to make
said next process the current process for execution after its scheduling
time occurs; and
message transmission means for effecting synchronized message transmission
between concurrent processes, said message transmission means comprising a
plurality of communication channels, a storage apparatus for storing a
status indicator to indicate the status of data communication through each
channel, and synchronizing means responsive to said status indicator to
stop executing a current process or add a process to a collection awaiting
execution so that communication between two communicating processes is
completed when the two processes are at corresponding program steps.
2. A microcomputer comprising memory, a timer and a processor coupled to
read from and write into said memory, said processor being configured to
execute a plurality of concurrent processes in accordance with a plurality
of program steps, at least some of said processes being time dependent
said time dependent process including a time-related instruction including
a time value relative to said timer:
(a) the microcomputer including a scheduling system comprising (i) a
time-ordered linked list of processes awaiting execution by the processor
after a scheduling time for each process in said list, (ii) a set of
storage locations associated with said linked list for indicating a
scheduling time when the processes in said list becomes ready for
execution, and (iii) an addressable storage element for indicating the
process which is currently being executed by the processor, said process
being referred to as the current process, (iv) a control system coupled to
said time-ordered linked list for adding a further process thereto at a
time-ordered position between a preceding process having an earlier
scheduling time and a following process having a later scheduling time,
(v) a next process indicator to indicate the next process on said
time-ordered list, and (vi) a program stage indicator for each concurrent
process; and
(b) said memory providing for each process a respective workspace having a
plurality of addressable locations, each of said work spaces for a process
on said time-ordered list including (i) first memory locations for
recording variables associated with the corresponding process, (ii) a
second memory location for said program stage indicator for the
corresponding process, (iii) a third memory location for indicating the
next process on said time-ordered linked list;
whereby when said processor executes a time-related instruction, said
processor compares said time-related instruction to the time indicated by
said timer, and, in response to said time-related instruction having
arrived in said timer, continuing execution of said current process; in
response to said time value in said time related instruction having not
yet arrived, stopping execution of said current process and causing said
control to add said current process to said collection.
3. A microcomputer comprising memory and a processor coupled to read from
and write into said memory, said processor being configured to execute a
plurality of concurrent processes in accordance with a plurality of
program steps, at least some of said processes being time dependent:
(a) the microcomputer including a scheduling system comprising (i) a time
ordered linked list of processor after a scheduling time for each process
in said list, (ii) a set of storage locations associated with said linked
list for indicating a scheduling time when the processes in said list
becomes ready for execution, and (iii) an addressable storage element for
indicating the process which is currently being executed by the processor,
said process being referred to as the current process, (iv) a control
system coupled to said time-ordered linked list for adding a further
process thereto at a time-ordered position between a preceding process
having an earlier scheduling time and a following process having a later
scheduling time, (v) a next process indicator to indicate the next process
on said time-ordered list, and (vi) a program stage indicator for each of
said concurrent processes;
(b) said memory providing for each process a respective workspace having a
plurality of addressable locations, each of said work space for a process
on said time-ordered lists including (i) first memory locations for
recording variables associated with the corresponding process, (ii) a
second memory location for said program stage indicator for the
corresponding process, (iii) a third memory location for indicating the
next process on said time ordered linked list; and
(c) the microcomputer further including message transmission means for
effecting synchronized message transmission between concurrent processes,
said message transmission means comprising a plurality of communication
channels, a status indicator for indicating the status of data
communication through each channel, and synchronizing means responsive to
the status indicator to a current process or add a process to a collection
awaiting execution so that communication between two communicating
processes is completed when the two processes are at corresponding program
steps.
4. A network of directly interconnected microcomputers each comprising a
timer and a single integrated circuit microcomputer comprising memory and
a processor arranged to execute a plurality of concurrent processes in
accordance with a plurality of program steps, said program steps
comprising a plurality of instructions for sequential execution by the
processor, some of said plurality of instructions being time related, said
time related instructions including a time value relative to said timer,
each said microcomputer including a scheduling system comprising:
(i) an addressable storage element for indicating the process which is
being executed by the processor, said process being referred to as the
current process;
(ii) a timer list for identifying one or more processes which form a
time-ordered collection awaiting execution by the processor after
respective scheduling times for each process in said collection;
(iii) a set of storage locations associated with said timer list for
storing data to indicate respective scheduling times when the processes in
said collection becomes ready for execution;
(iv) a control system coupled to said timer list for adding a further
process to said collection at a time-ordered position between a preceding
process having an earlier scheduling time and a following process having a
later scheduling time;
(v) a next process indicator to indicate the next process in said
time-ordered collection for execution by the processor; and
(vi) a program stage indicator for each concurrent process;
said processor further including a logic circuit responsive to said next
process indicator to make the next process in said collection the current
process for execution after its scheduling time occurs; whereby when said
processor executes a time-related instruction, said processor compares
said time-related instruction to the time indicated by said timer, and, in
response to said time-related instruction having arrived in said timer,
continuing execution of said current process; in response to said time
value in said time related instruction having not yet arrived, stopping
execution of the current process and causing said control to add said
current process to said collection.
5. A network of directly interconnected microcomputers each comprising a
single integrated circuit microcomputer comprising memory and a processor
arranged to execute a plurality of concurrent processes in accordance with
a plurality of program steps, said program steps comprising a plurality of
instructions for sequential execution by the processor, each said
microcomputer including a scheduling system comprising:
(i) an addressable storage element for indicating the process which is
being executed by the processor, said process being referred to as the
current process;
(ii) a timer list for identifying one or more processes which form a
time-ordered collection awaiting execution by the processor after
respective scheduling times for each process in said collection;
(iii) a set of storage locations associated with said timer list for
storing data to indicate respective scheduling times when the processes in
said collection becomes ready for execution;
(iv) a control system coupled to said timer list for adding a further
process to said collection at a time-ordered position between a preceding
process having an earlier scheduling time and a following process having a
later scheduling time;
(v) a next process indicator to indicate the next process in said
time-ordered collection for execution by the processor; and
(vi) a program stage indicator for each concurrent process, said processor
further including a logic circuit responsive to said next process
indicator to make the next process in said collection the current process
for execution after its scheduling time occurs; and
said microcomputer further including message transmission means for
effecting synchronized message transmission between concurrent processes,
said message transmission means comprising a plurality of communication
channels, a storage apparatus for storing a status indicator for
indicating the status of data communication through each channel, and
synchronizing means responsive to said status indicator to stop a current
process or add a process to a collection awaiting execution so that
communication between two communicating processes is completed when the
two processes are at corresponding program steps.
6. A method of operating concurrent processes, at least some of which are
time dependent processes, in a computer system wherein each concurrent
process executes a program having a plurality of instructions, comprising
the steps of:
forming a first pointer for each process to identify the process;
forming a second pointer for each process to indicate a program stage for
the process;
scheduling a plurality of processes for execution by one processor
including
providing an indication of a process which is being executed by said one
processor, said process being referred to as the current process;
identifying a time-ordered collection of processes each having a respective
scheduling time when the process may be executed by said one processor;
and
providing an indication of said scheduling time for each process in the
time-ordered collection, the process in said collection having the
earliest scheduling time being indicated as the next process;
wherein execution of said current process comprises executing a sequence of
instructions including a time related instruction indicating a scheduling
time before which the current process is not to continue execution and
responding to execution of said time related instruction by (a)
determining whether said scheduling time has yet arrived, (b) in response
to determining that the scheduling time has arrived, then continuing
execution of the said process, and (c) in response to determining that the
scheduling time has not yet arrived, (i) storing said second pointer for
the process, (ii) stopping execution of the said current process, (iii)
causing the said one processor which executed said time related
instruction to add the stopped process to said time-ordered collection at
a position in the time-ordered collection such that its scheduling time
forms an ordered sequence of scheduling times in the collection, and (iv)
setting the indication of the current process to indicate a further
scheduled process;
at a time after the scheduling time of said next process, responding to
execution of an instruction stopping the current process by setting the
indication of the current process to indicate the said next process and
executing said next process at a program stage indicated by the second
pointer for the said next process; and
transmitting messages between concurrent processes through a plurality of
addressable communication channels to permit data communication between
processes, wherein each process executes a sequence of instructions in a
program including communication instructions arranged to complete message
transmission between two processes when both are at corresponding program
stages.
7. A method according to claim 6 comprising operating concurrent processes
in a computer system comprising a network of interconnected integrated
circuit devices and wherein said step of transmitting messages between
concurrent processes is effected by addressing communication channels of a
first type to permit data communication between two processes both on the
same integrated circuit device and addressing channels of a second type to
permit data communication between processes wherein one process is on one
said integrated circuit device and the other process is on another
integrated circuit device.
8. A method of operating concurrent processes, at least some of which are
time dependent processes, in a computer system wherein each concurrent
process executes a program having a plurality of instructions, comprising
the steps of:
forming a first pointer for each process to identify the process;
forming a second pointer for each process to indicate a program stage for
the process;
scheduling a plurality of processes for execution by one processor
including
providing an indication of a process which is being executed by said one
processor, said process being referred to as the current process;
identifying a time-ordered collection of processes each having a respective
scheduling time when the process may be executed by said one processor;
and
providing an indication of said scheduling time for each process in the
time-ordered collection, the process in said collection having the
earliest scheduling time being indicated as the next process;
wherein execution of said current process comprises executing a sequence of
instructions including a time related instruction indicating a scheduling
time before which the current process is not to continue execution and
responding to execution of said time related instruction by (a)
determining whether said scheduling time has yet arrived, (b) in response
to determining that the scheduling time has arrived, continuing execution
of the said current process, and (c) in response to determining that the
scheduling time has not yet arrived, then (i) storing said second pointer
for the said current process, (ii) stopping execution of the said current
process, (iii) causing the said one processor which executed said time
related instructing to add the stopped process to said time-ordered
collection at a position in the time-ordered collection such that its
scheduling time forms an ordered sequence of scheduling times in the
collection, and (iv) setting the indication of the current process to
indicate a further scheduled process;
at a time after the scheduling time of said next process, responding to
execution of an instruction stopping the current process by setting the
indication of the current process to indicate the said next process and
executing said next process at a program stage indicated by the second
pointer for the said next process; and
executing a process having a plurality of alternative time related
components, indicating a time associated with each component, and
determining whether the time associated with any of the components has yet
occurred.
9. A method according to claim 8 further comprising descheduling the
process there defined if the earliest time associated with any of said
alternative time related components has not yet occurred and adding said
process to said time-ordered collection.
10. A method according to claim 8 further comprising loading into a memory
location for the current process a special value indicating the state of
the process and indicating that the process is one with alternative
components.
11. A method according to claim 10 further comprising loading into said
memory location a first special value to indicate that at least one of the
alternative components is ready and the process is to remain scheduled,
and loading a second special value into said memory location to indicate
that the process is descheduled while awaiting arrival of the time
associated with one of the alternative components.
12. A method according to claim 8 further comprising loading into a memory
location associated with the current process a special value to indicate
that none of the alternative components has yet been selected and
responding to said special value in order to select one of the alternative
process components when the process is scheduled.
13. A method according to claim 8 wherein said process includes a plurality
of alternative components at least some of which are time related, and
wherein at least one of said alternative components comprises inputting a
message through a communication channel, said method including determining
whether the earliest time of any time related component has yet occurred
and determining whether any communication channel is ready to input a
message.
14. A method of operating concurrent processes, at least some of which are
time dependent processes, in a computer system wherein each concurrent
process executes a program having a plurality of instructions, comprising
the steps of:
forming a first pointer for each process to identify the process;
forming a second pointer for each process to indicate a program stage for
the process;
scheduling a plurality of processes for execution by one processor
including providing an indication of a process which is being executed by
said one processor, said process being referred to as the current process;
identifying a time-ordered collection of processes each having a respective
scheduling time when the process may be executed by said one processor;
and
providing an indication of said scheduling time for each process in the
time-ordered collection, the process in said collection having the
earliest scheduling time being indicated as the next process;
wherein execution of said current process comprises executing a sequence of
instructions including a time related instruction indicating a scheduling
time before which the current process is not to continue execution and
responding to execution of said time related instruction by (a)
determining whether said scheduling time has yet arrived, (b) in response
to determining that the scheduling time has arrived, continuing execution
of the said process and (c) in response to determining that the scheduling
time has not yet arrived, (i) storing said second pointer for the said
current process, (ii) stopping execution of the said current process,
(iii) causing the said one processor which executed said time related
instruction to add the stopped process to said time-ordered collection at
a position in the time-ordered collection such that its scheduling time
forms an ordered sequence of scheduling times in the collection, and (iv)
setting the indication of the current process to indicate a further
scheduled process, and at a time after the scheduling time of said next
process, responding to execution of an instruction stopping the current
process by setting the indication of the current process to indicate the
said next process and executing said next process at a program stage
indicated by the second pointer for the said next process; and
specifying a time duration for the execution of a current process,
responding to said time duration to stop executing the current process
after expiry of the time duration, and rescheduling the process by adding
it to a scheduled collection.
15. A microcomputer comprising memory and a processor configured to execute
a plurality of concurrent processes by said processor in accordance with a
plurality of program steps, at least some of said processes being time
dependent, the microcomputer including a scheduling system comprising:
(i) an addressable storage element for indicating a current process which
is being executed by said processor, said process being referred to as the
current process;
(ii) a timer list coupled to said storage element for identifying one or
more processes which form a time-ordered collection awaiting execution by
said processor after respective scheduling times for the processes in said
collection;
(iii) a set of storage locations associated with said timer list for
indicating scheduling times when the processes in said collection become
ready for execution;
(iv) a control system coupled to said timer list and to said processor to
cause said processor to add a further process to said collection at a
time-ordered position between a preceding process having an earlier
scheduling time and a following process having a later scheduling time;
(v) a next process indicator to indicate the next process in said
time-ordered collection for execution by said processor;
(vi) a program stage indicator for each concurrent process; said processor
including timing logic responsive to said next process indicator to make
said next process the current process for execution after its scheduling
time occurs; and
the microcomputer further including one or more communication channels for
message transmission between concurrent processes and synchronizing means
for synchronizing message transmission through said channels.
16. The microcomputer according to claim 15 wherein said scheduling system
further includes means for identifying processes which form a scheduled
collection of processes awaiting execution by the processor and control
means for adding a process to said scheduled collection, said scheduling
system being responsive to said synchronizing means to terminate execution
of the current process or to add a process to said scheduled collection
thereby to achieve synchronization between concurrent processes.
17. The microcomputer according to claim 15 wherein said communication
channels include a communication link which can be connected by a
dedicated connection to a similar link on another device, thereby
permitting message transmission with synchronization between concurrent
processes on different microcomputers.
18. The microcomputer according to claim 15 wherein a process may execute
one of a number of alternative components at least one of which is time
related and at least one of which involves an input through one of said
communication channels, said microcomputer further including means for
determining whether the earliest time of any said time related component
has yet occurred and whether any of said communication channels is ready
yet to input a message.
19. A microcomputer comprising memory and a processor configured to execute
a plurality of concurrent processes by said processor in accordance with a
plurality of program steps, at least some of said processes being time
dependent, the microcomputer including a scheduling system comprising:
(i) an addressable storage element for indicating a process which is being
executed by said processor, said process being referred to as the current
process;
(ii) a timer list coupled to said storage element for identifying one or
more processes which form a time-ordered collection awaiting execution by
said processor after respective scheduling times for the processes in said
collection;
(iii) a set of storage locations associated with said timer list for
indicating scheduling times when the processes in said collection become
ready for execution;
(iv) a control system coupled to said timer list and to said processor to
cause said processor to add a further process to said collection at a
time-ordered position between a preceding process having an earlier
scheduling time and a following process having a later scheduling time;
(v) a next process indicator to indicate the next process in said
time-ordered collection for execution by said processor;
(vi) a program stage indicator for each concurrent process; said processor
including timing logic responsive to said next process indicator to make
said next process the current process for execution after its scheduling
time occurs,
(vii) means for identifying one or more processes which form a scheduled
collection of processes awaiting execution by the processor,
(viii) second means for adding a further process to said scheduled
collection, and
(ix) a second next process indicator to indicate the next process in said
scheduled collection to be executed by the processor, the processor being
responsive to selected instructions to terminate execution of the current
process and to respond to said second next process indicator to make the
process indicated therein the current process, whereby the processor is
operated to share its processing time between a plurality of concurrent
processes; wherein a process may execute one of a plurality of alternative
time related components, said microcomputer further comprising means to
indicate a time associated with each component, means to test the time
associated with each component, and means to determine whether the
earliest time associated with a component has yet occurred.
20. The microcomputer according to claim 19 wherein said scheduling system
further comprises means to cause descheduling of said process if said
earliest time has not yet occurred, and to cause said process to be added
to said time-ordered collection.
21. The microcomputer according to claim 20 further comprising means for
loading into a memory location corresponding to the process at least one
special value to indicate the state of the process and to indicate that
the process is one with alternative components.
22. The microcomputer according to claim 21 further comprising means for
storing in said memory location corresponding to said process a first
special value to indicate that at least one of the alternative components
is ready and that the process is to remain scheduled, or a second special
value to indicate that the process is descheduled while awaiting an
alternative component to become ready.
23. The microcomputer according to claim 19 further comprising means for
loading into a memory location corresponding to said process a special
value to indicate that none of the alternative components has yet been
selected, and means responsive to said special value to select one of the
alternative process components when the process is rescheduled.
24. A microcomputer comprising memory and a processor configured to execute
a plurality of concurrent processes by said processor in accordance with a
plurality of program steps, at least some of said processes being time
dependent, the microcomputer including a scheduling system comprising:
(i) an addressable storage element for indicating a process which is being
executed by said processor, said process being referred to as the current
process;
(ii) a timer list coupled to said storage element for identifying one of
more processes which form a time-ordered collection awaiting execution by
said processor after respective scheduling times for the processes in said
collection;
(iii) a set of storage locations associated with said timer list for
indicating scheduling times when the processes in said collection become
ready for execution;
(iv) a control system coupled to said timer list and to said processor to
cause said processor to add a further process to said collection at a
time-ordered position between a preceding process having an earlier
scheduling time and a following process having a later scheduling time;
(v) a next process indicator to indicate the next process in said
time-ordered collection for execution by said processor;
(vi) a program stage indicator for each concurrent process; said processor
including timing logic responsive to said next process indicator to make
said next process the current process for execution after its scheduling
time occurs;
(vii) means for identifying one or more processes which form a scheduled
collection of processes awaiting execution by the processor;
(viii) second means for adding a further process to said scheduled
collection;
(ix) a second next process indicator to indicate the next process in said
scheduled collection to be executed by the processor, the processor being
responsive to selected instructions to terminate execution of the current
process and to respond to said second next process indicator to make the
process indicated therein the current process, whereby the processor is
operated to share its processing time between a plurality of concurrent
processes;
(x) means for specifying a time duration for the execution of a process;
and
(xi) means responsive to said time duration to cause the processor to stop
executing the current process after expiration of said time duration and
to reschedule that current process by adding it to said scheduled
collection.
25. A microcomputer comprising a memory and a processor configured to
execute a plurality of concurrent processes in accordance with a plurality
of program steps, at least some of said processes being time dependent,
including:
a storage device for indicating the process which is currently being
executed by the processor, said process being referred to as the current
process;
a workspace for each process, said workspace including a plurality of first
memory locations for recording variables associated with the corresponding
process, a second memory location for indicating another process scheduled
for execution by the processor, said second memory locations thereby
collectively including a linked list of scheduled processes awaiting
execution, a third memory location for storing a program stage indicator
for the corresponding process, a fourth memory location for indicating the
next process on a time-oriented list of processes so that said fourth
memory locations collectively include a linked list of time-oriented
processes awaiting scheduling, said memory further providing fifth memory
locations for storing a respective time for each process on said linked
list of time-ordered processes;
a timing device responsive to time data from said fifth memory location;
a control device responsive to said timing device for adding a process to
said linked list of scheduled processes.
26. The microcomputer according to claim 25 wherein said fifth memory
locations are distributed in said workspaces for said processes.
27. The microcomputer according to claim 25 further comprising means for
indicating the process at the beginning of said time-oriented linked list,
and further including storage means for indicating the time data for the
process indicated by said first storage means.
28. A method of operating concurrent processes, at least some of which are
time dependent processes, in a computer system having a processor wherein
each concurrent process executes a program having a plurality of
instructions, said processor including a timer comprising the steps of:
forming a first pointer for each process to identify the process,
forming a second pointer for each process to indicate a program stage for
the process,
providing an indication of a process which is being executed by said
processor, said process being referred to as the current process,
identifying a time-ordered collection of time dependent processes each
having a respective specified scheduling time when the process may be
executed by said processor,
providing an indication of said specified scheduling time for each process
in the time-ordered collection, the process in said collection having the
earliest said specified scheduling time being indicated as the next
process,
and wherein execution of said current process comprises executing a
sequence of instructions including a time related instruction indicating a
specified scheduling time before which the current process is not to
continue execution and responding to execution of said time related
instruction by (a) comparing said specified scheduling time to the time
indicated by said timer in said processor to determine whether said
specified scheduling time has yet arrived, (b) in response to determining
that the specified scheduling time has arrived, continuing execution of
the said current process, and (c) in response to determining that the
specified scheduling time has not yet arrived, (i) storing said second
pointer for the process, (ii) stopping execution of the said current
process, (iii) causing the said processor which executed said time related
instruction to add the stopped process to said time-ordered collection at
a position in the time-ordered collection such that its specified
scheduling time forms an ordered sequence of specified times in the
collection, and (iv) setting the indication of the current process to
indicate a further process, and at a time after the specified scheduling
time of said next process, responding to the execution of an instruction
stopping the current process by setting the indication of the current
process to indicate the said next process at a program stage indicated by
the second pointer for the said next process.
29. A method of operating concurrent processes, at least some of which are
time dependent processes, in a computer system having at least one
processor, said processor including a timer and memory wherein each of
said concurrent processes executes a plurality of instructions included in
respective programs, the method comprising the steps of:
(a) establishing within the memory a respective workspace for each process,
each workspace comprising a plurality of addressable memory locations, and
recording in said locations of each workspace variables associated with
the corresponding process;
(b) defining a respective first pointer for each process to identify the
process;
(c) defining a respective second pointer for each process to indicate a
program stage for the process; and
(d) scheduling a plurality of processes for execution by said one
processor, including (i) providing an indication of a process which is
being executed by said one processor, said process being referred to as
the current process, (ii) forming a timeordered linked list of processes
awaiting execution by the processor after a respective specified
scheduling time indicated for each process in said list, said linked list
being formed by providing in the workspace of each process in the list an
indication of a specified scheduling time for the process, and an
indication of said first pointer for the process with the next specified
scheduling time,
and wherein execution of said current process comprises executing a
sequence of instructions including a time related instruction indicating a
specified scheduling time before which the current process is not to
continue execution and responding to execution of said time related
instruction by (a) comparing said specified scheduling time to the time
indicated by said timer in said processor to determine whether said
specified scheduling time has yet arrived, (b) in response to determining
that the specified scheduling time has arrived continuing execution of the
said current process, and (c) in response to determining that the
specified scheduling time has not yet arrived (i) storing said second
pointer for the process, (ii) stopping execution of said current process,
(iii) causing the said one processor which executed said time-related
instruction to add the stopped process to said time-ordered collection at
a position in the time-ordered collection such that its specified
scheduling time forms an ordered sequence of specified scheduling times in
the collection, (iv) setting the indication of the current process to
indicate a further scheduled process, and (v) at a time after the
specified scheduling time of said next process, responding to execution of
an instruction stopping the current process by setting the indication of
the current process to indicate said next process and executing said next
process at a program stage indicated by the second pointer for the said
next process.
30. The method according to claim 29 further comprising adding a further
process to said linked list by the steps of indicating a scheduling time
for said further process, examining the scheduling times of processes
already on the list, and adding said further process to the list at a
time-ordered position dependent on its scheduling time, said further
process being inserted between a preceding process and a following process
by providing in the workspace of said preceding process an indication of
said first pointer of said further process and providing in the workspace
of said further process an indication of said first pointer of the
following process.
31. A method of operating concurrent processes, at least some of which are
time dependent processes, in a computer system wherein each concurrent
process executes a program having a plurality of instructions, said
computer system including a timer, comprising the steps of:
forming a first pointer for each process to identify the process;
forming a second pointer for each process to indicate a program stage for
the process;
scheduling a plurality of processes for execution by one processor
including providing an indication of a process which is being executed by
said one processor, said process being referred to as the current process;
identifying a time-ordered collection of processes each having a respective
specified scheduling time when the process may be executed by said one
processor; and
providing an indication of said specified scheduling time for each process
in the time-ordered collection, the process in said collection having the
earliest scheduling time being indicated as the next process;
wherein execution of said current process comprises executing a sequence of
instructions including a time related instruction indicating a specified
scheduling time before which the current process is not to continue
execution and responding to execution of said time related instruction by
(a) comparing said specified scheduling time to the time indicated by said
timer in said computer system to determine whether said specified
scheduling time has yet arrived, (b) in response to determining that the
specified scheduling time has arrived, then continuing execution of the
said current process, and (c) in response to determining that the
specified scheduling time has not yet arrived, (i) storing said second
pointer for the current process, (ii) stopping execution of the said
current process, (iii) causing the said one processor which executed same
time-related instruction to add the stopped current process to said
time-ordered collection at a position in the time-ordered collection such
that its scheduling time forms an ordered sequence of scheduling times in
the collection, and (iv) setting the indication of the current process to
indicate a further scheduled process, and
at a time after the specified scheduling time of said next process,
responding to execution of an instruction stopping the current process by
setting the indication of the current process to indicate the said next
process and executing said next process at a program stage indicated by
the second pointer for the said next process.
32. A method according to claim 31 wherein the current process continues
execution without stopping when on execution of a time related instruction
the step of determining whether said scheduling time has yet arrived
indicates that the scheduling time has already arrived.
33. The method according to claim 31 wherein said scheduling step further
comprises identifying a scheduled collection of processes awaiting
execution by the processor and wherein said next process is added to said
scheduled collection and removed from said time-ordered collection after
its scheduling time.
34. The method according to claim 31 further comprising the steps of
indicating a priority for each process and establishing first and second
time-ordered collections of processes, said first collection comprising
processes of a common first priority and said second collection comprising
processes of a common second priority different from said first priority.
35. A method according to claim 31 wherein said next process on a
time-ordered collection is removed therefrom when its scheduling time
arrives and the process on the time-ordered collection with the next
scheduling time is then indicated as the next process.
36. A method according to claim 31 further comprising executing a current
process having a program sequence including a time dependent instruction,
determining a scheduling time associated with said instruction, and
continuing to execute the current process if said scheduling time has
already been reached.
37. A microcomputer comprising a timer, memory and a processor configured
to execute a plurality of concurrent processes by said processor in
accordance with a plurality of program steps, at least some of said
processes being time dependent, said time dependent processes including
time-related instructions, said time-related instruction including a time
value relative to said timer, the mic | | |
