A geometric data correction method is applicable to geometric data-element data comprising a plurality of line segments and circular arcs. When geometric data elements that should originally be interconnected cross or become separated from each other, the offset between geometric data elements is corrected automatically. This saves a great amount of time in comparison with that needed for redrawing of the geometric data elements. The method includes a topology recognition step of recognizing the topology of the geometric data elements, a geometric-parameter alteration step of correcting the offset of geometric data elements by altering geometric parameters, which define each geometric data element, with regard to all geometric data elements while maintaining the topology thereof, and an end-point decision step of deciding end points accompanied by enlargement/reduction of the geometric data elements. The method may further include a parameter-setting step of setting a connection parameter, which is necessary in order to obtain at least the connected state between geometric data elements, and a maximum amount of alteration of the geometric parameters of the geometric data elements, or an error-information output step of outputting error information generated at the geometric-parameter alteration step.

Visualization of how multiple constraints may effect design implementation choices and characterization of design spaces is provided by a system for computer aided design of a higher level electronic system which is itself constructed from lower level entities. A plurality of violation free regions is defined, with each region being determined by a particular entity-to-entity spacing rule or rule set. The multiplicity of violation free regions define ranges of valid position placements for entities within a particular constraint domain. Multiple constraint domains are handled by defining additional violation free regions which determine ranges of valid position placements for entities which satisfy the various additional constraint domains. The various violation free regions are logically combined to define a resulting violation free volume in which a component may be placed which will satisfy the constraints of all of the constraint domains whose violation free regions have been logically combined.

A tool changer system is disclosed comprising one or more tool grippers together with a pressure foot insert change pod supported on a U-V slide which is independent of the machine work table. The slide services a tool magazine mounted on the machine tool in close proximity to the work table. Because the tool changer is independent of the machine table, the selection and retrieval of the next tool to be used is performed while the machine tool is working. Similarly, the replacement of the tool back into its storage location is done while the machine tool is working. The exchanging of the pressure foot insert is done as part of the tool change process. Time is saved because the work table does not have to be moved to position the tool changer under the spindle. In fact, the work table may be moved to the next work location while the tool changer changes the tool in the spindle. An alternative embodiment of this invention avoids complex adjustment of certain types of tools when loading the same into the machine spindle where the precise location of the tool tip is unknown. Such adjustment occurs whenever tools without positioning collars are stored in the magazine. The instant invention permits such adjustment "off line" while the machine tool is working on an work piece by including a new dual piston gripper mechanism and a coarse axial adjustment pad thereby saving additional time and increasing the output of the machine. Also shown in the patent is a cartridge for tool magazines which accepts the EURO cassette without the need to separately unload tools from the cassette and load the typical tool cartridge.

Patterns for a routable interface of the signal lines of a integrated circuit device include several groups of terminals distributed about the pattern center, each group clustered along a corresponding curvilinear reference segment extending outward from the pattern center to its perimeter. Routability zones are created between each successive pair of groups. For higher terminal density, in at least one of the terminal groups of the pattern, either the offset of the terminals from the reference line segment is not uniform, or the distance of the terminals from the pattern center does not increase uniformly. A portion, preferably at least about 50% of the terminals in a group of the pattern are not collinear with, but offset from, the reference segment. A portion, preferably at least about 90% of the terminals in a given terminal group are each closer to the reference line segment of that terminal group than they are to the reference segment of another terminal group. The patterns of this invention can be employed on IC chips, IC package layers and PCB layers for patterning of terminals, pins, via, pads and another connector devices useful in IC devices.

Patterns for a routable interface of the signal lines of a integrated circuit device include several groups of terminals distributed about the pattern center, each group clustered along a corresponding curvilinear reference segment extending outward from the pattern center to its perimeter. Routability zones are created between each successive pair of groups. For higher terminal density, in at least one of the terminal groups of the pattern, either the offset of the terminals from the reference line segment is not uniform, or the distance of the terminals from the pattern center does not increase uniformly. A portion, preferably at least about 50% of the terminals in a group of the pattern are not collinear with, but offset from, the reference segment. A portion, preferably at least about 90% of the terminals in a given terminal group are each closer to the reference line segment of that terminal group than they are to the reference segment of another terminal group. The patterns of this invention can be employed on IC chips, IC package layers and PCB layers for patterning of terminals, pins, via, pads and another connector devices useful in IC devices.