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Claims  |
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We claim:
1. Apparatus for testing an electronic circuit, said tester having a
plurality of tester channels, each channel operating independently of all
other channels, each channel comprising:
a test pins means for contacting a test point of a unit under test;
a channel control circuit means coupled to said pin for controlling the
state of operation of said pin; and
a pin memory circuit means for storing test instructions which direct the
sequence of operation of said channel control circuit, said pin memory
circuit means being controlled by said channel control circuit means for
cycling said pin memory means to a next address only when a new test
instruction is required for that channel independent of a state of
operation of all other channels.
2. The tester of claim 1 wherein channel control circuit means includes:
a pin driver for driving said pin with a predetermined signal; and
a data receiver for receiving data from said test point.
3. The tester of claim 2 wherein said pin driver circuit is a tri-state
logic circuit, a high impedance output state being selected when said
channel control circuit is instructed to receive data from said test
point.
4. The tester of claim 2 further comprising a clock generator circuit means
generating a clock signal coupled to each channel control circuit means,
each channel control circuit means cycling said memory, when required, in
synchronism with said clock signal.
5. The tester of claim 4 wherein said clock generator is coupled to a
central processor which controls the operation of said tester, said
central processor controlling said clock generator circuit to generate a
signal which starts a test sequence for all channels.
6. The tester of claim 2 wherein said test pins are driven with a digital
signal and said received data is a digital signal.
7. The tester of claim 1 wherein each pin memory circuit means is a random
access memory (RAM).
8. The tester of claim 7 wherein each pin memory circuit means is a dynamic
random access memory (DRAM).
9. The tester of claim 8 wherein the size of said pin memory means is not
identical for each channel.
10. In a multichannel tester for an electronic circuit having in each
channel a test pin for contacting a test point of a unit under test and a
pin memory circuit for storing instructions which determine a state of
operation of said test pin, a channel control circuit means coupled
between said test pin and an output of said pin memory, said channel
control circuit means comprising:
means coupled to the output of said pin memory for decoding an instructions
presented at said output; pin controlling means coupled to said decoding
means for controlling the state of operation of said pin in response to a
control signal from said decoding means;
means coupled to said decoding means for generating the address of the next
instruction in said pin memory, said address generator cycling said memory
to said next address only when a new instruction is required to change the
state of operation of that channel.
11. The circuit of claim 10 wherein said channel control circuit means
includes:
a pin driver for driving said pin with a predetermined signal; and
a data receiver for receiving data from said test point.
12. The circuit of claim 11 wherein said pin driver circuit is a tri-state
logic circuit, a high impedance output state being selected when said
channel control circuit is instructed to receive data from said test
point.
13. The circuit of claim 10 wherein said memory address generator cycles
said memory in synchronism with a clock signal which is common to all
channels of said tester.
14. The circuit of claim 13 wherein said decoder and pin controller operate
in synchronism with said clock signal.
15. The circuit of claim 14 wherein the frequency of said clock signal is
substantially 100 MHz.
16. The circuit of claim 14 wherein said decoder and said address generator
are responsive to a start/stop signal which starts a test sequence
consisting of a sequence of test instructions in said pin memory in
synchronism with said start/stop signal and stops said test sequence in
synchronism with said start/stop signal in all channels of said tester.
17. The circuit of claim 16 wherein said pin memory is a dynamic random
access memory (DRAM) circuit.
18. In a multichannel tester for an electronic circuit having in each
channel a test pin for contacting a test point of a unit under test and a
pin memory circuit for storing test instructions which determine the state
of operation of said test pin, a channel control circuit means coupled
between said test pin and an output of said pin memory circuit, said
channel control circuit means comprising:
programmable timing means responsive to the output of said pin memory for
timing a desired interval between a present state of operation of said
test pin and a next state of operation of said pin; and
memory address generator means coupled to said timing means for generating
the address of a next instruction is said pin memory, said memory being
cycled to said next address at the end of said programmed time.
19. The circuit of claim 18 wherein said channel control circuit includes:
a pin driver for driving said pin with a predetermined signal; and
a data receiver for receiving data from said test point.
20. The circuit of claim 19 wherein said pin driver circuit is a tri-state
logic circuit, a high impedance output state being selected when said
channel control circuit is instructed to receive data from said test
point.
21. The circuit of claim 18 wherein said memory address generator cycles
said memory in synchronism with a clock signal which is common to all
channels of said tester.
22. The circuit of claim 21 wherein said channel control circuit includes a
decoder coupled to the output of said pin memory for decoding an
instruction presented at said output and a pin controller for controlling
the state of operation of said pin in response to a control signal from
said decoder, said decoder and pin controller operate in synchronism with
said clock signal.
23. The circuit of claim 22 wherein said decoder and said address generator
are responsive to a start/stop signal which starts a test sequence
consisting of a sequence of test instructions in said pin memory in
synchronism with said start/stop signal and stops said test sequence in
synchronism with said start/stop signal in all channels of said tester.
24. The circuit of claim 22 wherein the frequency of said clock signal is
substantially 100 MHz.
25. The circuit of claim 18 wherein said pin memory is a dynamic random
access memory (DRAM) circuit.
26. Apparatus for testing an electronic circuit, said tester having a
plurality of tester channels, each channel operating independently of all
other channels, said each channel comprising:
a test pin means for contacting a test point of a unit under test;
a pin memory circuit means for storing test instructions which direct the
state of operation of said test pin; and
a channel control circuit means coupled between said pin and an output of
said pin memory means for controlling the state of operation of said pin
in response to test instructions appearing at said pin memory output, said
channel control circuit means including programmable timer means
responsive to instructions appearing at said pin memory means output to
time a desired interval between a present state of operation of said test
pin and a next state of operation of said pin; and
means coupled to said timing means for generating the address of a next
instruction in said pin memory means, said memory being cycled to said
next address at the end of said programmed time.
27. The circuit of claim 26 wherein said channel control circuit means
includes:
a pin driver for driving said pin with a predetermined signal; and
a data receiver for receiving data from said test point.
28. The circuit of claim 27 wherein said pin driver circuit is a tri-state
logic circuit, a high impedance output state being selected when said
channel control circuit is instructed to receive data from said test
point.
29. The circuit of claim 26 wherein said memory address generator cycles
said pin memory means in synchronism with a clock signal which is common
to all channels of said tester.
30. The circuit of claim 21 wherein said channel control circuit includes a
decoder coupled to the output of said pin memory for decoding an
instruction presented at said output and a pin controller for controlling
the state of operation of said pin in response to a control signal from
said decoder, said decoder and pin controller operate in synchronism with
said clock signal.
31. The circuit of claim 29 wherein said decoder and said address generator
are responsive to a synch signal which starts a test sequence consisting
of a sequence of test instructions in said pin memory in synchronism with
said synch signal and stops said test sequence in synchronism with said
start/stop signal in all channels of said tester.
32. The circuit of claim 30 wherein the frequency of said clock signal is
substantially 100 MHz.
33. The circuit of claim 26 wherein said pin memory means is a dynamic
random access memory (DRAM) circuit.
34. The circuit of claim 26 further comprising shift register means for
converting the output of said pin memory means from a parallel to a serial
format, to produce a bit stream which is coupled to said programmable
timing means.
35. A multichannel tester for an electronic circuit, each channel being
controlled by a sequence of test instructions stored in a memory circuit
and operated independently of all other channels, said each channel,
comprising:
means for cycling said memory to a next address to obtain a new test
instruction;
means for decoding said new test instruction to determine the next state of
operation by a channel, said decoding being dependent on the present state
of operation of that channel. |
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Claims |
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Description |
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This invention relates to a method and apparatus for the automatic testing
of electronic circuits. In particular, it relates to the automatic
functional testing of electronic circuits on a printed circuit board.
Functional testers are connected to the input/output connector of the
printed circuit board, by means of an edge connector which mates with the
circuit board when it is inserted into the fixture of the automatic
testing apparatus. The functional tester exercises the board so as to
simulate the actual functioning of the printed circuit board in its
intended environment. The tester measures data which represent the outputs
of the printed circuit board circuit, compares them against the expected
result and determines whether or not the printed circuit board is
functioning properly in its intended environment. Hence the name
"functional tester".
FIG. 1 illustrates a prior art apparatus generally indicated as 100 for
functionally testing a unit under test (UUT) 146. For clarity of
illustration, the tester 100 is shown as having only three channels,
whereas testers with 256 or 512 channels are common. Each pin of the
tester, here labelled pins .phi., 1 and n, contact the corresponding pin
on the connector of the UUT. Each pin is connected in turn to the output
of an interface circuit 140, 142 or 144 which contains a driver to drive
the pin with predetermined signals and a receiver for receiving data from
the pin. This interface circuit is known in the art as the "pin
electronics". The pin electronics can drive the pin with a digital signal
which is either high or low to represent a digital "1" or "0". In
addition, the driver circuit can be placed in a high impedance output
state and a receiver circuit can be activated to measure the data on the
pin to determine whether or not the voltage on the pin is high or low
thereby representing a digital "1"or a digital "0".
The pin electronics 140, 142, 144 are each connected to the output of a
channel control circuit 126, 128, 130, respectively, by output buses 134,
136 and 138. The operation of the channel control circuits is directed by
instructions stored in a pin control random access memory (RAM) 114, 116
or 118, there being one such memory for each channel of the tester. The
test instructions stored in the pin control RAM determine if the pin is to
be driven or an input of data is to be taken from the pin. In addition, it
determines whether the pin is to be driven high or low or if data is to be
received whether the data is expected to be high or low. The test
instructions from the pin RAM also determine which of the global timing
signals are utilized to produce an output or receive an input at a
particular pin, as will be explained in detail below. The pin RAMs are
controlled by a global sequence control processor 104 which generates an
address onto address bus 112 which is coupled to all of the pin RAMs in
the tester. The global sequence control processor 104 is controlled by a
sequence control RAM 102 via bus 106 to implement the test program stored
in sequence control RAM 102. The instructions of the program in the
sequence control RAM 102 cause the global sequence control processor to
generate a new address which in turn cycles all of the pin RAMs to a new
address thus enabling a change in state on all of the channels of the
tester. The fact that the pin RAMs function as a single memory with all
RAMs cycling to the same next address at the same time allowed some prior
art testers to utilize a single memory circuit in place of individual pin
RAMs. The only requirement on this memory circuit is that it have a long
enough word (or memory "width") to provide the required number of control
bits to the input of each channel control circuit at the same time in
parallel. The test program stored in sequence control RAM 102 may, for
example, comprise a sequence of steps which is repeated for a given number
of times. These program instructions cause the global sequence control
processor to generate a sequence of addresses which implements the
repetition of these steps. The address bus 112 is also coupled to the
input of the sequence control RAM 102 and the input of a timing control
RAM 111. The address present on this bus is utilized to fetch the next
instruction from RAM 102 to control the global sequence control processor
104 and the next instruction from RAM 111 to control the operation of
global timing control generator 110. The select instructions from RAM 111
are coupled to generator 110 via bus 108.
The global sequence control processor 104 operates in synchronism with a
clocking signal generated by global timing control generator 110 and
coupled to the global sequence control processor by line 109. The clocking
signal is controlled by timing control information stored in the timing
control RAM 111 to change the memory word provided to the channel control
circuits 126, 128, 130 for each pin at every interval. The operation of
the unit under test may dictate that all of the changes in the state of
operation of the pin not occur simultaneously. The minimum amount of time
between changes in the state of operation is generally limited by the
cycle time of the memory in the pin RAM, which as a practical matter is
too long to permit the required flexibility of activity within a cycle.
Accordingly, the changes in operation are controlled by a series of timing
signals produced by the global timing control generator 110 and coupled to
the channel control circuits by timing signal bus 132. A typical global
timing control generator may be able to produce eight sets of eight
different signals each with only one of the eight sets being generated at
any given time. Accordingly, timing signal bus 132 will be eight lines
wide and have eight timing signals present at any given time. The
selection of the particular set of timing signals that is to be generated
at any given time is changeable "on the fly" under the control of the
select information stored in the timing control RAM 111. The selection is
made via select bus 108. Thus, the instructions contained in the pin RAMs
do not merely dictate the change in state of operation of a pin but also
specify the timing pulse at which the actual change in state will occur.
That is, the instructions in the memory will cause the change in the state
of operation of the pin to occur on a selected transition of the selected
one of the eight timing pulses. For example, the timing information could
go high on timing signal three, which means that the pin would be driven
to a high state on the low-to-high transition of timing signal three.
Programming flexibility for the test sequences is provided by having the
instructions stored in timing control RAM 111 control the set of timing
pulses produced and the length of time between memory cycles. This permits
maximizing the number of activities that can take place on all of the pins
per memory cycle without unduly limiting the ability to change the state
of any given pin.
In some prior art testers, the timing signals are generated within each
channel control circuit to provide greater flexibility in performing the
test sequence. However, the small number of timing signals available still
places limitations on the ability of the tester to simulate the actual
operating environment of the unit under test.
Functional testers employing this type of architecture have several major
disadvantages. Firstly, it is desirable to have the drive/read signals
correspond exactly to signals which are expected during the normal
operation on the printed circuit board. The fact that there are only eight
timing signals (or some other small number) available means that
compromises must be made in producing signals which can be close enough to
all of the desired timing functions throughout the test of the circuit.
For example, if we had to perform one operation 5 nanoseconds after the
clock pulse and another operation 4 nanoseconds after the clock pulse and
had only a single timing signal remaining which had to be used to control
both of these operations, then a compromise would have to be made. We
would have to either decide which of the timing intervals was more
critical to the operation of the circuit or, perhaps choose an interval of
say 4.5 nanoseconds as a compromise. Even if a larger number than eight
signals were provided, compromises would obviously still have to be made
in programming the test. This unnecessarily complicates the generation of
the test, especially for large/complex circuit boards. Because of the
complexity of the implications created by the various trade off
possibilities, the programming of a test for a functional tester has
remained a manual task. Manually programming a precise test for a
large/complex circuit can take longer and be more costly than is
practical. Accordingly, compromises are usually made to reduce the effort
and cost although this results in a less accurate test. This problem will
be exacerbated by the increasingly complex circuit boards of the future.
Increasing the number of operations that can take place between memory
cycles would ease the problem but requires more bits per word and thus
increases the size of the memory.
Another disadvantage of this prior art technique is that many times a pin
is very active during a portion of the test and relatively quiet during
the remainder of the test. However, since the memory address for all pins
must be updated for a single pin-event as well as a string of pin-events,
the memory locations for these relatively quiet pins must be filled with
no operations (no-ops). This is extremely wasteful of expensive memory
space. Furthermore, in order to improve the efficiency of programming
these tests, it has been common to allow for looping of the test program.
This requires the use of static random access memories (SRAMs) which are
relatively expensive. In testers that do utilize the lower cost dynamic
random access memories (DRAMs), portions of the program are typically
periodically loaded into SRAMs for execution. A further disadvantage of
this architecture is the fact that parallel address and timing buses run
throughout the tester electronics because they must be connected to all
electronics for all of the pins, thus creating problems of time skew
between bits in these lines at higher memory speeds.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide an improved
automatic test system architecture and a method for operating same.
Another object of the invention is to provide an automatic test system
having a "true tester-per-pin" architecture.
A further object of the invention is to provide an automatic test system in
which the pin memory is cycled to the next address only when a test
instruction is required to change the state of operation of that channel.
Yet another object of the present invention is to provide an automatic test
system in which the pin memory is cycled to the next address at the end of
a programmed time.
A further object of the present invention is to provide an automatic test
system which utilizes dynamic random access memory circuits for storing
the test instructions.
Another object of the present invention is to provide an automatic test
system which utilizes dynamic random access memory circuits for storing
the test instructions and which permits backward loops in the sequence of
test instructions.
A further object of the present invention is to provide an automatic test
system in which the decoding of the test instructions to determine the
next state of operation of a channel is dependent upon the present state
of operation of that channel.
These and other objects, advantages and features are achieved by apparatus
for testing an electronic circuit, having a plurality of tester channels.
Each channel of the tester has a test pin means for contacting a test
point of a unit under test; a channel control circuit means coupled to
said pin for controlling the state of operation of said pin; and a pin
memory circuit means for storing test instructions which direct the
sequence of operation of said channel control circuit, said pin memory
circuit means being controlled by said channel control circuit means to
cycle said pin memory means to a next address only when a new test
instruction is required for that channel.
Another aspect of the invention includes a method for operating a
multichannel tester for an electronic circuit having in each channel a
test pin for contacting a test point of a unit under test and a pin memory
circuit for storing instructions which determine the state of operation of
said test pin. The pin memory circuit is cycled to a next address only
when a new test instruction is required to change a state of operation of
that channel.
A further aspect of the invention includes a multichannel tester for an
electronic circuit having in each channel a test pin for contacting a test
point of a unit under test and a pin memory circuit for storing
instructions which determine a state of operation of said test pin. A
channel control circuit is coupled between said test pin and an output of
said pin memory circuit. The channel control circuit includes means
coupled to the output of said pin memory for decoding an instruction
presented at said output; means coupled to said decoding means for
controlling the state of operation of said pin in response to a control
signal from said decoding means; and means coupled to said decoding means
for generating the address of the next instruction in said pin memory. The
address generator cycles said memory to said next address only when a new
instruction is required to change the state of operation of that channel.
Another aspect of the invention comprises a multichannel tester for an
electronic circuit having in each channel a test pin for contacting a test
point of a unit under test and a pin memory circuit for storing test
instructions which determine the state of operation of said test pin. A
channel control circuit is coupled between said test pin and an output of
said pin memory circuit. The channel control circuit includes a
programmable timing means responsive to the output of said pin memory for
timing a desired interval between a present state of operation of said
test pin and a next state of operation of said pin and means coupled to
said timing means for generating the address of a next instruction in said
pin memory. The memory is cycled to said next address at the end of said
programmed time.
A still further aspect of the invention includes a method for operating a
multichannel tester for an electronic circuit having in each channel a
test pin for contacting a test point of a unit under test and a pin memory
circuit storing test instructions which determine the state of operation
of said test pin, and a channel control circuit coupled between said test
pin and an output of said pin memory circuit. A timer is programmed
utilizing instructions appearing at said output of said pin memory circuit
to time a desired interval between a present state of operation of said
test pin and a next state of operation of said pin. The pin memory circuit
is cycled to a next address to a new test instruction for said next state
of operation of said test pin.
Another aspect of the invention includes an apparatus for testing an
electronic circuit having a plurality of tester channels Each channel
includes a test pin means for contacting a test point of a unit under
test, a pin memory circuit means for storing test instructions which
direct the state of operation of said test pin, a channel control circuit
means coupled between said pin and an output of said pin memory means for
controlling the state of operation of said pin in response to test
instructions appearing at said pin memory output, said channel control
circuit means including programmable timer means responsive to
instructions appearing at said pin memory means output to time a desired
interval between a present state of operation of said test pin and a next
state of operation of said pin, and means coupled to said timing means for
generating the address of a next instruction in said pin memory means,
said memory being cycled to said next address at the end of said
programmed time. Yet another aspect of the invention comprises an
apparatus for testing an electronic circuit having a plurality of tester
channels, each channel having a channel control circuit for controlling
the state of operation of said channel in response to a sequence of test
instructions stored in a respective memory circuit. The memory circuit
includes a dynamic random access memory (DRAM) circuit means for storing
said test instructions, and a cache memory circuit means coupled to said
DRAM circuit and to said channel control circuit for storing a subsequence
of test instructions from said DRAM circuit; said channel control circuit
controlling the operation of said channel from the test instructions
stored in said cache memory means while refreshing said DRAM circuit,
thereby permitting backward loops in said sequence of test instructions.
A further aspect of the invention includes a method for operating a
multichannel tester for an electronic circuit having a plurality of
channels, each channel having a channel control circuit for controlling
the state of operation of said channel in response to a sequence of test
instructions stored in a respective dynamic random access memory (DRAM)
circuit. Backward loops in said sequence of test instructions are
permitted by storing a subsequence of test instructions from said DRAM
circuit in a cache memory circuit and operating said channel from the test
instructions in said cache memory while simultaneously refreshing said
DRAM circuit.
Another aspect of the invention comprises a method of operating a
multichannel tester for an electronic circuit, each channel being
controlled by a sequence of test instructions stored in a memory circuit.
The memory is cycled to a next address to obtain a new test instruction
and the new test instruction is decoded to determine the next state of
operation by a channel, said decoding being dependent on the present state
of operation of that channel.
A still further aspect of the invention includes a multichannel tester for
an electronic circuit, each channel being controlled by a sequence of test
instructions stored in a memory circuit. A means for cycling said memory
to a next address to obtain a new test instruction. A means for decoding
said new test instruction to determine the next state of operation by a
channel, said decoding being dependent on the present state of operation
of that channel.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a prior art shared resource system;
FIG. 2 is a block diagram of one embodiment of a system in accordance with
the present invention;
FIG. 3 is a more detailed block diagram of a channel control circuit in
accordance with the invention shown in FIG. 2;
FIG. 4 is a block diagram of the RAM data decoder shown in FIG. 3;
FIG. 5 is a timing diagram illustrating a typical test sequence on one pin
of the tester in accordance with the present invention;
FIG. 6 is a block diagram of a channel control circuit which includes a
cache memory.
DETAILED DESCRIPTION
Referring to FIG. 2, a functional tester in accordance with the present
invention is generally shown as 200. As in FIG. 1, the tester is shown as
having three channels, .phi., 1 and n, for clarity of illustration,
whereas it is common to have testers with 256, 512 or more channels. The
tester is again organized so that each channel has its respective pin RAM
channel control circuit and pin electronics. Thus, pin RAM 210 is coupled
to channel control 224 via instruction bus 222 and address bus 220 and
channel control 224 is coupled to pin electronics 238 via lines 240, 242
and 244 to form channel .phi.. Similarly, pin RAM 212 is coupled to
channel control 230 via instruction bus 228 and address bus 226 and
channel control 230 is coupled to pin electronics 252 via lines 254, 256,
258 to form channel 1; pin RAM 214 is coupled to channel control 236 via
instruction bus 234 and address bus 232 and channel control 236 is coupled
to pin electronics 266 via lines 268, 270, 272 to form channel N. Each of
the channel control circuits are coupled to their respective connector pin
which are brought into contact with the connector of the unit under test
(UUT) 280. Thus, pin electronics 238 is coupled to pin .phi. via line 250,
pin electronics is coupled to pin 1 via line 264 and pin electronics 266
is coupled to pin N via line 278.
In the illustrated embodiment, the pin electronics is suitable for
sink/source logic circuits such as TTL or CMOS. Each contains a driver
circuit which can be placed in a high impedance (tri-state) output state
and a receiver circuit. Other logic families would require different pin
electronics.
In the embodiment illustrated in FIG. 2, the pin electronics 238 for
channel .phi. comprises a tri-state driver 246 coupled to the channel
control 224 by line 244. Driver 246 can be placed in a high impedance
output state by means of a signal on line 242. A data receiver 248 is
coupled to pin .phi. by line 250 and to channel control 224 by line 240.
Similarly, the pin electronics 252 for channel 1 comprises driver 268 and
receiver 262. Driver 268 is coupled to channel control 230 by line 258 and
can be place in a nigh impedance state by a signal on line 256. Data
receiver 262 is coupled to pin by line 264 and to channel control 230 by
line 254. The pin electronics 266 for channel N comprises driver 274 and
receiver 276. Driver 274 is coupled to channel control 236 via line 272
and can be placed in a high impedance state by a signal on line 270.
The pin electronics 238, 252, 266 may be coupled to the channel controls
224, 230, 236 by a line carrying encoded instructions instead of the
technique illustrated in FIG. 2. This is because the pin electronics are
located very close to the UUT in order to preserve the integrity of the
drive or received signals whereas the remainder of the electronics may be
in another portion of the tester and coupled to the pin electronics by a
cable which is relatively long in view of the high operating speeds. The
encoded signals would be decoded and perform the same functions shown in
FIG. 2. The details of such an arrangement are well known to those skilled
in the art and need not be repeated here.
Each of the pin RAMs 210, 212, 214 are coupled to the central processor 202
by means of an instruction bus 208. The central processor 202 is also
coupled to a clock generator 206 by means of control line 204. The clock
generator 206 generates a clock signal which is present on line 216 and
coupled to all of the channel control circuits within the tester. Clock
generator 206 also generates a synchronizing (hereinafter "synch") signal
which is present on line 218 and also coupled to all of the channel
control circuits in the tester.
Although each of the pin RAMs receive an input from a bus which is common
to all of the RAMs, similar to circuits shown in FIG. 1, it should be
carefully noted that the common bus in FIG. 2 is an instruction bus
whereas the common bus in FIG. 1 is an address bus. The instruction bus
shown in FIG. 2 is used prior to the test to be performed by the tester.
During this phase of operation, it is necessary to load the instructions
to be performed during the test into each of the pin RAMs. The central
processor 202 addresses each of the pin RAMs by means not shown and loads
the instructions which perform the desired test into the pin RAM.
Alternatively, bus 208 could be connected to all of the channel
controllers and the instructions loaded into the pin RAMs by the channel
controllers. The instructions provided on instruction bus 208 could come
from the memory associated with the central processor 202 but more
commonly will come from a magnetic tape or disk, although other sources
could obviously be used. After the central processor 202 has loaded the
instructions into all of the pin RAMs in the tester, the instruction bus
208 plays no further part in the operation of the tester. It should also
be noted that the tester shown in FIG. 1 also requires this means of
initially loading the instructions into the pin RAMs, and that this has
been omitted from FIG. 1 for clarity of illustration.
Accordingly, once the tester 200 has been loaded with the test program,
there is no centralized control over the address utilized to fetch an
instruction from the pin RAM. The address for each pin RAM is sent over
its respective address bus from its respective channel control circuit For
example, in channel .phi., the address for pin RAM 210 is provided over
address bus 220 from channel control 224. Thus, the generation of the
address for channel .phi. is independent of the address generation for all
other channels in the tester. This in turn eliminates the need to cycle
each pin RAM in order to generate the required test sequence. The channel
control therefore only cycles the memory when it is necessary to obtain a
new instruction for changing the state of that channel which greatly
reduces the amount of data that must be stored in the tester in order to
generate the test sequence. The detailed operation of the channel control
circuit will be described in connection with FIGS. 3, 4, 5 and 6. The
ability to operate each channel independent of the other so that the
memory need only be cycled when it is necessary to obtain a new test
instruction to modify the state of operation of that channel makes each
channel, in effect, an independent tester. Accordingly, the architecture
of this tester may be referred to as a "true tester-per-pin" architecture.
A feature of this architecture is that the size of each of the pin RAMS
need not be identical because the RAMS will not be cycled together. Some
channels may have larger pin RAMS than the others, these channels being
reserved for more active pins.
Each channel of the tester operates :n the same manner although
independently. Referring to channel .phi. as an example, channel control
circuit 224 will produce an address on bus 220 when it is necessary to
fetch a new instruction from pin RAM 210 in order to change the state of
operation of channel .phi.. The new instruction is sent to channel control
224 via instruction bus 222 from pin RAM 210. Channel control 224 decodes
the instruction to determine whether or not pin driver 246 is to be
activated. If driver 246 is to be activated to drive the pin to a high or
low state, the appropriate signal is placed at the input of the driver and
the pin is driven to either a high or a low state as required by the test
instruction. If the driver is not to be activated but data is to be
received via receiver 248, then a signal is provided on line 242 to place
the output of the tri-state logic driver 246 into its high impedance
state. In this state, the driver 246 has no effect on the signal being
received by the data receiver 248. If data is to be received, it will be
compared against the expected value of that data and the results sent to
the central processor by means not shown.
Although each channel operates independently, all channels operate in
synchronism with a clock signal provided on line 216. The clock signal
shown in FIG. 2 is a typical clock signal that might be utilized for this
system having, for example, a 100 MHz rate with a 5 nanosecond segment in
the high state and a 5 nanosecond segment in the low state. This signal is
continuously generated and all memory cycles would occur on the leading
edge of the clock signal on line 216. Synchronization is obviously
required because it :s necessary that the data change in accordance with
the protocol (operating requirements) of the circuits, particularly
integrated circuit logic and microprocessors, utilized on the electronic
circuit board. As the clock signal is continuously generated, it is
necessary that the test sequence on all pins be started or stopped in
synchronism. Accordingly, a line 218 is provided with a synch signal which
:s generated by clock generator 206 under control of the central processor
202 via control line 204. The test sequence is started for all channels on
the leading edge of the synch signal which occurs in the middle of a clock
period so that all channels will start on the next clock edge. A time
monitor in clock generator 206 keeps track of the length of the test and
stops the test sequence by changing the state of the synch signal. It
should be noted that two short pulses, one to start the test and another
to stop the test, could be used in place of the single long pulse
illustrated.
FIG. 3 shows a more detailed block diagram of a channel control circuit
224, 230 or 236, generally shown as 300. The channel control circuit has a
RAM data decoder 304 which is coupled to the pin RAM via instruction bus
302. The instruction bus would correspond to bus 222, 228 or 234 in FIG.
2. The RAM data decoder 304 is also coupled to a memory address generator
308 via line 310. Memory address generator 308 is in turn coupled to the
pin RAM, such as RAM 210, 212 or 214 via address bus 306 which
corresponds, for example, to buses 220, 226 or 232. RAM data decoder 304
is coupled to a pin control circuit 320 via data buses 312 and 314. Pin
control circuit 320 is coupled to pin electronics 334 via lines 322, 324
and 326. The pin electronics comprises a pin driver 330 coupled to pin
control circuit 320 via line 326. The tri-state input of driver 330 is
coupled to the pin control circuit 320 via line 324. Pin control 320
receives data from a data receiver 328 via line 322. Data receiver 328 and
pin driver 330 are coupled together via a line 332 which is also coupled
to the respective test pin of that channel. RAM data decoder 304, memory
address generator 308 and pin control 320 are connected to the clock
generator 206 via line 316. RAM data decoder 304 and memory address
generator 308 are also connected to the synch signal generator in clock
generator 206 via line 318.
RAM data decoder 304 receives a word from the output of the pin RAM via
instruction bus 302. This word is the next instruction in the test
sequence for that channel and will change the state of operation of that
channel and only that channel. The RAM data decoder 304 decodes this word
to generate a data word which determines the type of event that will take
place on the pin coupled to that channel of the tester. The RAM data
decoder 304 also decodes the instruction to produce a word which
determines the timing of the event which will be explained in detail
below. A detailed description of the operation of decoder 304 will be
presented below in conjunction with FIG. 4. Pin control 320 utilizes the
event data word and timing data word to generate signals to the pin
electronics 334 to drive the pin connected to the UUT or to receive data
from the UUT. The major difference between pin control 320 and a
corresponding portion of the channel control circuits of the prior art is
that pin control 320 is programmable to generate the required timing
information for each pin event. In the prior art, the electronics selected
one of a predetermined number of timing signals which either were
externally generated for all of the channels of the tester or internally
generated for each channel of the tester in accordance with instructions
loaded into each channel at the start of the test. Neither prior art
system provided, therefore, the flexibility to have the timing for each
pin event independent of any other pin event in the test sequence. It is
this flexibility that allows the tester to follow exactly the test pattern
required for the UUT and also permits the memory reduction described
above. The generation of a typical test sequence for one pin of a tester
will be discussed below in connection with FIG. 5 and Table 1.
Memory address generator 308 generates the address of the next instruction
to be retrieved from the pin RAM for that channel. This address is coupled
to the pin RAM via bus 306 which corresponds, for example, to the buses
220, 226 and 232 of FIG. 2. The memory address generator is responsive to
a signal from RAM data decoder 304 coupled via line 310 to generate the
next memory address. In the embodiment shown, looping in the test sequence
in order that a portion of the sequence be repeated a predetermined number
of times, is not provided. This is discussed below in conjunction with
FIG. 6.
FIG. 4 shows a more detailed block diagram of the RAM data decoder 304,
generally shown as 400. The data bus 302 is shown as bus 402 which, as
illustrated, is 80 bits wide. The width of data bus 402 is determined by
the cycle time of the pin RAMs and the time resolution that is desired.
For example, if it is desirable to use DRAMs having a cycle time of 80
nanoseconds and if we want a resolution of 1 nanosecond per bit, this
yields a word width of 80 bits. Although a wide word is required, the
system is still very cost effecti | | |
