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System and method for sharing resources of a host computer among a plurality of remote computers    
United States Patent4994963   
Link to this pagehttp://www.wikipatents.com/4994963.html
Inventor(s)Rorden; Randall J. (Orem, UT); Arthur; Ronald B. (Provo, UT); Rex; Michael E. (Orem, UT); Stewart; Darryl J. (Provo, UT); Muhlestein; Mark (Orem, UT); Fairclough; Dennis A. (Orem, UT)
AbstractA system for providing a high speed digital communication path between the processor of a host computer and the processors of one or more remote computers. The high speed digital communication path allows a remote computer to efficiently share the resources of the larger host computer such as high speed magnetic disk drives and printers. A host interface located at the host computer is connected to the internal host bus of the host computer. The host interface includes a host port and components which provide for the transfer of data from the host bus to the host port. The data bits presented at the host port are arranged in a parallel format. A communication cable conveys the parallel data bits from the host port to a remote port in a remote interface at a remote computer. The remote interface provides a random access memory and components for transferring data from the remote bus to the random access memory and vice-versa. Data bits presented at the remote port are also conveyed to the random access memory. The host interface and the remote interface include control structures to supervise and arbitrate accesses to the communication cable and to the random access memory.
   














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Drawing from US Patent 4994963
System and method for sharing resources of a host computer among a

     plurality of remote computers - US Patent 4994963 Drawing
System and method for sharing resources of a host computer among a plurality of remote computers
Inventor     Rorden; Randall J. (Orem, UT); Arthur; Ronald B. (Provo, UT); Rex; Michael E. (Orem, UT); Stewart; Darryl J. (Provo, UT); Muhlestein; Mark (Orem, UT); Fairclough; Dennis A. (Orem, UT)
Owner/Assignee     Icon Systems International, Inc. (Orem, UT)
Patent assignment
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Publication Date     February 19, 1991
Application Number     07/266,381
PAIR File History     Application Data   Transaction History
Image File Wrapper   Patent Term   Fees
Litigation
Filing Date     November 1, 1988
US Classification     710/305
Int'l Classification     G06F 015/16
Examiner     Zache; Raulfe B.
Assistant Examiner    
Attorney/Law Firm     Workman, Nydegger & Jensen
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USPTO Field of Search     364/200
Patent Tags     sharing resources host computer among a plurality remote computers
   
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What is claimed and desired to be secured by United States Letters Patent is:

1. A high speed digital communication system for linking a first digital processor connected to a first bus and a second digital processor connected to a second bus, the system comprising:

first port means for presenting digital data in a parallel configuration;

first control means for conveying digital data between the first bus and the first port means;

second port means for presenting digital data in a parallel configuration;

memory means for receiving all digital data presented to the second port means destined for the first digital processor and for receiving all data presented on the first bus destined for the second digital processor;

second control means for directing flow of designated data among the second port means, the memory means, and the second bus; and

interconnecting means for establishing a parallel digital communication path between the first port means and the second port means for rapidly transferring digital data between the first bus and the second bus to permit high speed communication between the first and second digital processors.

2. A high speed digital communication system as defined in claim 1 wherein the first port means comprises:

a plurality of differential line drivers; and

a plurality of differential line receivers.

3. A high speed digital communication system as defined in claim 2 wherein the plurality of differential line drivers and differential line receivers are connected in parallel.

4. A high speed digital communication system as defined in claim 1 wherein the first port means comprises a number of differential line drivers and wherein the interconnecting means comprises a number of paired conductors, the number of differential line drivers and the number of paired conductors being at least as great as whatever maximum number of bits of digital data is to be transferred between the first digital processor and the second digital processor in a parallel configuration.

5. A high speed digital communication system as defined in claim 4 wherein the first port means comprises a plurality differential line receivers and a terminating resistance connected across each pair of conductors in the interconnecting means connected to each differential line receiver.

6. A high speed digital communication system as defined in claim 1 wherein the first port means, the second port means, and the interconnecting means each comprises a plurality of control signal paths and a parallel data transmission path of at least 16-bits in width.

7. A high speed digital communication system as defined in claim 1 wherein the interconnecting means comprises a cable having at least 16 twisted pairs of conductors.

8. A high speed digital communication system as defined in claim 7 wherein the first port means and the second port means each comprise a connector having at least 32 conductors.

9. A high speed digital communication system as defined in claim 1 wherein the first bus includes an upper and a lower byte and wherein the system further comprises means for selectively swapping the upper and lower bytes of digital data being directed to and received from the first bus.

10. A high speed digital communication system as defined in claim 9 wherein the means for swapping the upper and lower bytes comprises:

a first set of buffers having their inputs and outputs connected such that the upper and lower bytes of digital data are passed straight through the first set of buffers;

a second set of buffers having their inputs and outputs connected such that the upper and lower bytes of digital data are swapped while passing through the buffers; and

a control line connected to the first control means, the control line determining whether the first set or second set of buffers is active.

11. A high speed digital communication system as defined in claim 1 comprising a plurality of first port means.

12. A high speed digital communication system as defined in claim 11 further comprising means for selecting one of the plurality of first port means from an address presented on the first bus.

13. A high speed digital communication system as defined in claim 1 wherein the first bus sequentially contains an address followed by digital data destined for the address and wherein the system further comprises means for sequentially multiplexing to the first port means the address and the digital data presented on the first bus.

14. A high speed digital communication system as defined in claim 1 wherein the system further comprises means for checking for digital data transmission errors.

15. A high speed digital communication system as defined in claim 14 wherein the means for checking for digital data transmission errors comprises a parity generator circuit and a parity check circuit.

16. A high speed digital communication system as defined in claim 1 wherein the memory means comprises a dual-ported random access memory.

17. A high speed digital communication system as defined in claim 1 wherein the memory means comprises:

a random access memory;

a first buffer connected between the random access memory and the second bus in order to allow the transfer of digital data between the random access memory and the second bus; and

a second buffer connected between the random access memory and the second port means in order to allow the transfer of digital data between the random access memory and the second port means.

18. An interprocessor communication system for establishing a communication path between at least one remote processor connected to a remote bus in a remote computer and a host processor connected to a host bus in a host computer, the communication system comprising:

means for providing at least one host data port at the host computer, the host data port comprising a plurality of data transfer lines arranged in a parallel configuration;

means for establishing a digital communication path between the host bus and the means for providing at least one host data port;

means for providing a remote data port at the remote processor, the remote data port comprising a plurality of data transfer lines arranged in a parallel configuration;

means for storing digital data received from and destined for the means for providing a remote data port;

first means for transferring data between the remote bus and the means for storing;

second means for transferring data between the means for storing and the means for providing a remote data port; and

means for interconnecting the means for providing a host data port and the means for providing a remote data port to create a parallel data path therebetween and to provide for bidirectional data flow between the host bus and the remote bus for high speed exchange of digital data between the host processor and the remote processor.

19. An interprocessor communication system as defined in claim 18 wherein the means for providing a remote data port comprises:

a plurality of differential line drivers; and

a plurality of differential line receivers.

20. An interprocessor communication system as defined in claim 19 wherein the plurality of differential line drivers and the plurality of differential line receivers are connected in parallel.

21. An interprocessor communication system as defined in claim 18 wherein the means for providing a remote data port comprises a number of differential line drivers and wherein the means for interconnecting comprises a number of paired conductors, the number of differential line drivers and the number of paired conductors being at least as great as the number of bits of digital data to be transferred between the remote processor and the host processor in a parallel configuration.

22. An interprocessor communication system as defined in claim 21 wherein the means for providing at least one host port comprises a plurality of differential line receivers and a terminating resistance connected across each pair of conductors in the interconnecting means connected to each differential line receiver.

23. An interprocessor communication system as defined in claim 18 wherein the means for providing at least one host data port, the means for providing a remote data port, and the means for interconnecting each comprises a plurality of control signal paths and a parallel data transmission path of at least 16-bits in width.

24. An interprocessor communication system as defined in claim 18 wherein the means for interconnecting comprises a cable having at least 16 twisted pairs of conductors and an outer diameter of less than one-half inch.

25. An interprocessor communication system as defined in claim 24 wherein the means for providing at least one host port and the means for providing a remote port each comprise a connector having at least 32 conductors.

26. An interprocessor communication system as defined in claim 18 wherein the host bus includes an upper and a lower byte and wherein the system further comprises means for selectively swapping the upper and lower bytes of digital data being directed to and received from the host bus.

27. An interprocessor communication system as defined in claim 26 wherein the means for swapping the upper and lower bytes comprises:

a first set of buffers having their inputs and outputs connected such that the upper and lower bytes of digital data are passed straight through the first set of buffers;

a second set of buffers having their inputs and outputs connected such that the upper and lower bytes of digital data are swapped while passing through the buffers; and

a control line connected to the means for establishing a digital communication path, the control line determining whether the first set or second set of buffers is active.

28. An interprocessor communication system as defined in claim 18 further comprising a plurality of host data ports and means for selecting one of the plurality of host data ports from the address presented on the host bus.

29. An interprocessor communication system as defined in claim 18 wherein the host bus sequentially contains an address followed by digital data destined for the address and wherein the system further comprises means for sequentially multiplexing the address and the digital data presented on the host bus to the means for providing at least one host data port.

30. An interprocessor communication system as defined in claim 18 wherein the system further comprises means for checking for digital data transmission errors.

31. An interprocessor communication system as defined in claim 30 wherein the means for checking for data transmission errors comprises a parity generator circuit and a parity check circuit.

32. An interprocessor communication system as defined in claim 18 wherein the means for storing digital data comprises:

a random access memory;

a first buffer connected between the random access memory and the remote bus in order to allow the transfer of digital data between the random access memory and the remote bus; and

a second buffer connected between the random access memory and the remote data port in order to allow the transfer of digital data between the random access memory and the remote data port.

33. A system for allowing resources of a host computer to be shared with a remote computer, the system comprising:

remote port means at the remote computer for receiving and transmitting digital data in a parallel configuration;

memory means at the remote computer for temporarily storing digital data received from and destined to the remote port means;

remote computer control means for (a) controlling the passage of digital data between the memory means and the remote port means, and for (b) controlling passage of digital data between the memory means and an internal bus of the remote computer;

host port means at the host computer for receiving and transmitting digital data in a parallel configuration;

control means for controlling passage of digital data between the host port means and an internal bus of the host computer; and

cable means for interconnecting the remote port means and the host port means for rapidly transferring digital data between said internal bus of the host computer and said internal bus of the remote computer, the cable means bidirectionally transmitting digital data in a parallel configuration.

34. A system for exchanging digital data between internal structures of a larger host computer and a plurality of remote computers, the system comprising:

(a) a host computer interface comprising:

(i) a plurality of host ports, each of the host ports configured to transmit and receive digital data in a parallel mode;

(ii) a host address circuit for directing data contained on the bus of a host computer to said addressed host ports; and

(iii) a multiplexing circuit for sequentially passing a portion of address and digital data presented on said bus of the host computer to the host port;

(b) a remote computer interface at each remote computer, each remote computer interface comprising:

(i) a remote port configured to transmit and receive digital data in a parallel mode;

(ii) a random access memory connected to the remote port for temporary storage of the data directed to and received from the remote port; and

(iii) control and address circuits for controlling transfer of digital data between a remote bus and the random access memory by allowing data placed on said remote bus of the remote computers to address the random access memory; and

(c) a communication cable connected between said plurality of host ports and the remote port in a parallel configuration for communicating digital data presented at one of said host ports or the remote port and thereafter communicating said digital data to the other port, the communication cable comprising a plurality of pairs of conductors, each pair of conductors conveying one data bit of a byte of digital data presented at the host computer at the remote port.

35. A method for communicating digital data between a host computer and at least one remote computer, the method comprising the steps of:

conveying the digital data from a bus of the host computer to a host port, the digital data being presented in a parallel configuration at the host port;

communicating in a parallel configuration to a remote port located at the remote computer the digital data presented at the host port;

storing the digital data communicated to the remote port;

interrupting the remote computer to request access to a bus of the remote computer; and

transferring the stored digital data to the bus of the remote computer, thereby establishing a high speed communication path between the bus of the host computer and the bus of the remote computer.

36. A method as defined in claim 35 wherein the step of conveying data comprises the steps of sequentially conveying an address and conveying digital data to the host port.

37. A method as defined in claim 35 further comprising the step of swapping byte order on the host bus.

38. A method as defined in claim 35 wherein the step of communicating the data comprises the step of communicating each data bit on an individual one of a plurality of conductors.

39. A method as defined in claim 35 wherein the step of communicating the data comprises the step of differentially driving a pair of conductors for each data bit.

40. A method as defined in claim 35 wherein the step of storing the data comprises the step of entering the digital data in a random access memory.

41. A method as defined in claim 40 wherein the step of transferring the data comprises the step of transferring eight-bit bytes of data from the random access memory to said bus of the remote computer.

42. A method as defined in claim 40 further comprising the steps of:

transferring digital data presented on the bus of the remote computer to the random access memory;

presenting the digital data in the random access memory to the remote port;

communicating to the host port in a parallel configuration the digital data presented at the remote port;

interrupting the host computer to request access to the bus of the host computer; and

conveying the digital data communicated to the host port to the host bus.

43. A method as defined in claim 42 wherein the host port and the remote port are interconnected by a cable and wherein the method further comprises the step of arbitrating between the host computer and the remote computer access to the random access memory.
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BACKGROUND

1. The Field of the Invention

This invention relates to systems and methods for transferring digital data within computer systems. More particularly, the present invention pertains to a high speed communication path that allows one or more remote computers to share the resources of a high speed host computer, thereby increasing the speed of operation of the remote computers.

2. The Background Art

Modern digital computers have become essential to business, science, industry, and military operations throughout the industrial world. In particular, the widespread availability of microcomputers, also often referred to as "personal computers", has made digital computers accessible to more people than ever before.

The affordability and widespread use of the microcomputer has caused a myriad of different microcomputer application programs to become available directed to those tasks that the microcomputer is best adapted. Many such applications, however, require the additional power of a mini or mainframe computer system unavailable in a microcomputer. Thus, many facilities are equipped with both a powerful mainframe or minicomputer, as well as a plurality of remote microcomputers located on the site.

Disadvantageously, the operating systems, architectures, and standards that have been developed for the microcomputer have differed from those developed for larger computer systems In view of the desire to retain efficient operations, these differences have made the interfacing of the different types of computers quite difficult.

Moreover, the internal and peripheral devices used with larger computers are often faster than the corresponding devices associated with each of the microcomputers. For example, while it is not generally economical to provide each microcomputer with a high capacity, fast-access magnetic hard disk drive memory device, it is effective to provide such a magnetic hard disk drive in connection with a mini or mainframe computer. Also, it is common for a high speed, high quality printer to be associated with a mini or mainframe computer, while not with a microcomputer.

Large computer systems often have excess space on their disk drive memory. Also, the printers associated with larger computers often sit idle much of the time. For these reasons, and because it is generally desirable to allow remote microcomputers to communicate with larger host computers, there has been a yet unfulfilled need for an effective communication link between a plurality of remote microcomputers and a larger host computer, whereby the remote computers could utilize directly the resources of the host computer.

Unfortunately, previously available computer systems do not provide for communication between a remote and a host computer in a manner that permits the remote computer to efficiently use the resources of the host computer. For example, data transmission systems such as local area networks and terminal communication systems, utilize serial data communication techniques that transmit data bits between computers one at a time over cables. This severely limits the speed of communication making impractical the transmission of data on a "clock cycle" basis, which is necessary for memory accesses by a microprocessor. The arbitration and managing functions exercised by local area networks slow communications even further. Thus, it has long been a need in the art that a remote computer and a host computer be able to communicate fast enough to share resources efficiently.

In view of the foregoing, it would be advantageous to develop a system and method for allowing a remote computer to share the resources of a host computer by providing high speed communication between the two. It would be a further advance if such a system were to allow a remote computer to access the disk drive of a host computer as a virtual disk drive. It would further benefit the users of smaller computers to provide a communication system for allowing a plurality of remote computers to off-load printing tasks to a host computer and to allow a remote computer to organize files into virtual disk partitions in a host computer disk drive. A data communication system for allowing one or more networks of remote computers to share the resources of a host computer, such as sharing of printers and file transfer functions, would be even a further step forward.

OBJECTS AND BRIEF SUMMARY OF THE INVENTION

In view of the foregoing, it is a primary object of the present invention to allow one or more remote computers to share and access the resources of a host computer. Such resources could include, for example, a plurality of operating systems available on the host computer.

Yet another object of the present invention is to increase the overall throughput of one or more remote computers.

An additional object of the present invention involves allowing one or more remote computers to share a peripheral device, such as a printer, that is associated with a host computer.

It is a further object of the present invention to decrease disk access times for a plurality of remote computers.

The present invention also has an objective of providing a high-speed communication path between a host computer and a remote computer.

It is yet another object of the present invention to enable one or more networks of remote computers to share the resources of a single host computer.

Still another object of the present invention is to allow one or more remote computers to act independently of a host computer, or to act as virtual terminals for the host computer.

These and other objects of the present invention will be further appreciated by an examination of this disclosure and by practicing the invention.

The present invention provides a high-speed digital communication path between a host computer and at least one remote computer by establishing a communication path directly between the internal bus of a host computer and the internal bus of a remote computer. The system of the present invention may be described as an interprocessor communication system, since the communication link established is essentially between the central processor of a host computer and the central processor of a remote computer.

In the embodiment of the present invention disclosed herein a host interface is installed in the host computer and a remote interface is installed in each remote computer of the system. The host interface allows digital data and control signals on the bus of the host computer to be transferred between that host bus to one of several host ports located at the host interface. Similarly, the remote interface allows digital data and control signals to be transferred between the bus of each remote computer and a corresponding remote port located on the remote interface at that remote computer.

A cable interconnects one of the host ports to each remote port. The interconnecting cable includes a sufficient number of conductors as to convey control signals and transmit data in a parallel mode on individual pairs of conductors. The bus of the remote computer is effectively rendered an extension of the host bus through the host interface, the interconnecting cable, and the remote interface.

A multiplexing means is provided in the host interface to sequentially multiplex either an address or digital data that is to be presented at the host port and thereafter, by way of the interconnecting cable, to the remote port. Control means in the form of control circuits are provided on both the remote interface and the host interface.

An address select/decode circuit in conjunction with the control means of the host interface causes one of several host ports to be selected from an address presented on the bus of the host computer. Thus, the most significant bits of an address presented on the bus of the host computer serves to select which host port is to be accessed. The remaining bits of an address presented on the bus of the host computer are used to select a location in a memory means or random access memory, which in the preferred embodiments is located on the remote interface. In this manner, the host computer is able to address the remote computer as if it were any other logical device in association with the host computer.

In the preferred embodiment of the invention disclosed herein, the host control circuit also regulates the operation of a byte-swapping means, or byte-swapping data buffer, which corrects the ordering of data bytes to overcome differences between the byte ordering schemes of the remote and host computers.

As disclosed herein, the remote computer is an IBM model PC/AT, an IBM model PC/XT computer, or an equivalent. A remote interface is provided at each remote computer which includes one remote port that is connected to the interconnecting cable. The remote interface includes a random access memory which functions as a temporary storage location for digital data received from the host computer. Digital data destined to the host computer from the remote computer is also stored temporarily in the random access memory. Such digital data is transmitted to the host computer by way of the remote port, the interconnecting cable, and the host interface. A control circuit included in the remote interface regulates the transfer of digital data between the random access memory and the remote port and bus of the remote computer.

When digital data is being both received by and transmitted from the remote computer, accesses to the random access memory by the host and remote computers is interleaved. The structure and speed of operation of the interfaces produce virtually no delay in the system. The operation of both the host interface and the remote interface is thus transparent, not only to a user, but to the remote and host computers.

The structure of the remote interface, the host interface, and the cable interconnecting the two enables the remote computer to efficiently share the resources of the host computer and to carry out functions which it otherwise could not. With the present invention supplemented by suitable software, a remote computer can access the memory devices of a host computer and also share the use of peripheral devices, such as printers. Moreover, the present invention allows for efficient file transfers between different operating systems and establishes the remote computer as a very fast terminal for the host computer.

BRIEF DESCRIPTION OF THE DRAWINGS

In the description which follows, and in the accompanying drawings, some of the figures have been divided into two or more parts in order to increase their clarity. Where a figure has been divided into two or more parts, a number designation has been added as a suffix to the figure number for each part into which the figure has been divided. For example, in the detailed schematic diagram provided in FIG. 5, the figure has been divided into two parts designated as "FIG. 5-1" and "FIG. 5-2." In the case of figures which have been divided into two or more parts, the complete figure may be reassembled by placing the first part of the figure in an upper left position, the second part in an upper right position, and the third part in a lower right position. Boxed letters at the margins of a figure that has been divided into parts indicate electrical interconnections between the parts of that figure.

FIG. 1 is a schematic representation of one arrangement of a host computer and a plurality of remote computers interconnected by a preferred embodiment of the system of the present invention.

FIG. 2 is a schematic representation of one arrangement of a host computer and a local area network including a plurality of remote computers, one of which is interconnected to the host computer by the system of the present invention shown in FIG. 1.

FIG. 3 is a schematic representation of one arrangement of a host computer and a local area network including a plurality of remote computers, two of which are interconnected to the host computer by the system of the present invention shown in FIG. 1.

FIG. 4 is a block diagram representing the structure of the host interface of the system of the present invention shown in FIG. 1.

FIGS. 5-1 and 5-2 provide a detailed schematic diagram of the control circuit of the host interface represented in FIG. 4.

FIG. 6 is a block diagram showing the structure of the byte swapping data buffer of the system of the present invention represented in FIG. 4.

FIG. 7 is a block diagram showing the structure of the host ports of the system of the present invention represented in FIG. 4.

FIG. 8 is a block diagram representing the structure of the remote interface of the system of the present invention shown in FIG. 1.

FIGS. 9-1, 9-2, and 9-3 provide a detailed schematic diagram of the control circuit of the remote interface represented in FIG. 8.

FIG. 10 is a block diagram showing the structure of the remote port of the system of the present invention represented in FIG. 8.

FIG. 11 is a state machine diagram for the state machines implemented in the components shown in FIGS. 9-1, 9-2, and 9-3.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

In the following description, like structures will be identified by like reference characters. It is to be understood that the structures described herein merely represent a presently preferred embodiment of the invention. Thus, the present invention may be implemented in many ways and incorporated into many computer systems, other than those described herein.

General Overview

As indicated earlier, the need has long existed in the computer industry that one or more remote computer systems be able to share the resources of a host computer, such as magnetic disk drives and printers. High-speed, high-quality magnetic disk drives and printers are mechanical devices that are particularly expensive to acquire and maintain. Thus, it is important that a computer system make maximum use of these devices. Allowing a plurality of remote computers to share these resources is much more cost effective than providing each remote computer with its own magnetic disk drive and printer of the same capacity as that provided to the host computer.

The sharing of resources, such as disk drives and printers, between a host and remote computer requires, however, that a very fast communication path be established between the two. The present invention provides such a high-speed communication path in the form of an interface provided at both the host computer and each of the remote computers for enabling a high-speed, processor-to-processor communication path. This allows many other functions to be carried out which would otherwise not be possible.

FIG. 1 illustrates one possible application of the present invention. A host computer 10 is shown as being provided with a host interface 12 that is preferably fabricated on a single circuit board that is selectively insertable and removable from host computer 10.

In the illustrated embodiment, host interface 12 is provided with six (6) host ports 14A-14F. In the application represented in FIG. 1, each of host ports 14A-14F is connected individually by a corresponding one of interconnecting cables 16A-16F to individual remote interfaces 20A-20F, respectively. Each of remote interfaces 20A-20F is preferably fabricated on a distinct circuit board to allow for its easy installation into host computer 10. Remote interfaces 20C-20F are designed to be readily installed in a number of different remote computers, two of which are shown in FIG. 1 by way of illustration as remote computers 22A and 22B.

In the presently preferred embodiment of the invention, remote computers 22A and 22B are IBM model PC/AT or model PC/XT computers, their equivalent, or another work station which incorporates the expansion bus of the IBM model PC/AT or model PC/XT computers. While the embodiment described herein is particularly adapted for use with such remote computers, the present invention may be implemented in many different forms and used with many different host and remote computer systems.

The embodiment of the present invention represented in FIG. 1 affords many advantageous capabilities to a user and many different benefits. Among these are (1) a virtual disk function, (2) a virtual terminal function, (3) a file transfer function, and (4) a print spooling function. Each will be explained below.

Each remote computer 22A-22B is given access to the disk drive of the host computer 10. This is the virtual disk function carried out by the system of the present invention. Using appropriate software, the system shown in FIG. 1 makes it appear to the processor of remote computers 22A-22B that the disk drive of host computer 10 is internal to each respective remote computer 22A-22B. Thus, the system of the present invention is transparent to the central processing units of the host computer 10 and to remote computers 22A-22B.

In the embodiment of the inventive system shown in FIG. 1, remote computers 22A-22B utilize the MS-DOS operating system. In such an operating system each virtual disk drive of host computer 10 simply appears to remote computers 22A-22B as a different internal designated disk drive, such as drive C, drive D, and so forth. The virtual disk drive function provided by the present invention may be organized and partitioned as any other MS-DOS disk drive for easy access and information sharing.

The host disk drive can be a very large, fast and efficient device. For example, a host disk drive may use a disk cache scheme. In such a disk cache scheme, often accessed data is moved from disk into a dedicated random access memory where it can be accessed in much less time than if a disk access were required. Furthermore, multiple disk drives may be included in the host computer.

The communication path between the remote computers and the host computer is also fast. Therefore, the use of the virtual disk drive function allows a remote computer to effect disk drive accesses faster than might otherwise be possible using a disk drive internal to the remote computer. This results in responsive remote computer operation.

The virtual terminal function of the inventive system allows the remote computers 22A-22B to be connected to the central processing unit of host computer 10 and act as terminals thereof. The extremely fast communication path between host computer 10 and remote computers 22A-22B provides screen updates that are effectively instantaneous.

A file transfer function may also be efficiently carried out using the present invention. The file transfer function allows a user to easily move files between different operating system environments. For example, in the presently preferred embodiment, file transfers may be effected between the UNIX, PICK, and MS-DOS operating system environments.

With the high-speed communication pathway provided by the present invention between each remote computer 22A-22B and host computer 10, the sharing of a printer or "print spooling" may also be accomplished. This feature permits the sharing of expensive printing devices, such as laser printers. The spooling for each printer occurs on a first-come, first-served basis, and the data to be printed is stored in the file system of the host computer. The remote computers may thus continue processing without waiting for printing to be completed.

FIG. 2 illustrates the embodiment of the present invention shown in FIG. 1 adapted to allow a local area network (LAN) of remote computers to function more efficiently by affording to a network file server remote computer 22A access to the fast disk drive of host computer 10. Remote computers 22B, 22C, and 22D are the other computers in the network. Each remote computer 22A-22D is provided with a LAN card 26 which is connected to an active hub 24 by a plurality of LAN cables 28. One local area network preferably adapted for use with the present invention is available from Novell, Inc. of Provo, Utah as the NETWARE.RTM. 286 2.0a system.

In the data communication system illustrated in FIG. 2, file server remote computer 22A may be based on an Intel 80386 microprocessor. By utilizing the host disk drive according to the system of the present invention, file server remote computer 22A realizes up to a three-fold increase in throughput. In addition, delays which are often experienced in file transfers and data base applications are reduced. Furthermore, the present invention improves the performance of some application programs by an order of magnitude.

In FIG. 2, file server remote computer 22A is provided with a direct connection to the resources of host computer 10 through interconnecting cable 16A. A file on the host disk drive thus takes the place of the disk drive that would normally need to be resident on file server remote computer 22A. As files on the large host disk drive can be accessed at very high speed, the present invention allows the local area network to operate more efficiently.

FIG. 3 shows yet another arrangement of the present invention used in an alternate manner with the local area network already described. File server remote computer 22A continues to be connected to host computer 10 by way of interconnecting cable 16A. Another of the remote computers, a host gateway remote computer 22A, is also provided with a direct connection to the host computer through remote interface 20B and interconnecting cable 16B. With one remote computer serving as a file server remote computer to share the disk drive of the host computer, host gateway remote computer 22B functions as a gateway to allow all other remote computers 22C-22D connected to the local area network to have access to the resources of the host computer and exercise the advantageous functions mentioned earlier.

A number of remote computers can be added to a local area network, such as that provided by Novell, Inc. This not only allows a number of remote computers to have access to all other remote computers on the local area network, but by way of host gateway remote computer 22B, to also have access to the resources of host computer 10. Due to the speed at which data is transferred between host gateway remote computer 22B and host computer 10, the only delay experienced by the user of a remote computer on the local area network is due to the delay inherent in the local area network itself.

All of the above are possible because the present invention establishes a high-speed communication path between the host and the remote computers. While the inventive embodiment disclosed incorporates some network-like functions, it is not a substitute for a local area network, such as that represented in FIGS. 2 and 3. Rather, the presently preferred embodiment augments and enhances the functions of a local area network.

A specific structure of a presently preferred embodiment of the present invention will now be described as adapted for use with host computers available from Icon International, Inc. of Orem, Utah utilizing the Motorola MC 68020 microprocessor.

Host computers incorporating the MC 68020 microprocessor must include a host bus structure meeting minimum structural and operational requirements. Complete information concerning the MC 68020 microprocessor can be found in the publication entitled MC 68020 32-bit Microprocessor User's Manual, 2d. Ed. (1985), and later editions, which are available from Prentice Hall Publishers, which are incorporated herein by reference.

Particular information concerning the bus structure of the host computer systems available from Icon International, Inc. is available from documentation pertaining to each specific computer system and in United States patent application Ser. No. 074,310, which is incorporated herein by reference.

As will be explained shortly, extremely fast data transmission between a host computer and one or more remote computers is possible according to the teachings of the present invention by creating a parallel data transmission path from the host bus in the host computer to the remote bus in the remote computer. The use of the structures herein described to form this "bus-to-bus" communication pathway allows extremely fast data transfer between a host computer and one or more remote computers without the time-consuming bottlenecks often found in local area networks, bottlenecks resulting from time-intensive tasks such as packetization and network arbitration.

The Host Interface

FIG. 4 is a block diagram showing the structures of one embodiment of host interface 12 incorporating teachings of the present invention. Consistent with FIGS. 1-3, it is preferred that host interface 12 be placed on a single circuit board, and that six (6) host ports 110A-110F be provided on each board. Other numbers of host ports, as well as other configurations for the host interface, are considered to be within the scope of the present invention.

A host bus 100, including thirty-two (32) lines serving as address lines, thirty-two (32) lines serving as data lines, and other control lines, is the principle bus of host computer 10. The MC 68020 microprocessor is connected to host bus 100, and when access to a remote device is desired, the address of that device is first presented on host bus 100 followed by the presentation thereon of digital data from or destined to the addressed device. With a host computer 10 utilizing a MC 68020 microprocessor, the host bus structure is dictated by the requirements of the MC 68020 microprocessor.

Host interface 12 receives all thirty-two (32) of the address lines and sixteen (16) of the data lines contained on host bus 100. A control circuit 104 in host interface 12 receives bits 16-31 of the address by way of an upper address bus 130. The remaining address bits 0-15 are presented to a multiplexer 116 by way of a lower host address bus 126. As will be explained in greater detail shortly, bits 16-31 on upper host address bus 130 select one host port 110A-110F, while bits 0-15 on lower host address bus 126 are passed directly by way of multiplexer 116 to the selected host port 110A-110F for selecting one address of a location in the random access memory location provided on the remote interface.

For maximum efficient and versatile operation, each host port 110A-110D provided in host interface 12 is addressed as a logical device, just as any memory space is addressed in the logical memory space of host computer 10.

In the inventive embodiment using the host computers previously identified, address space has been reserved for host interface 12 beginning at hexadecimal address E0000000 and extending through hexadecimal address E0FFFFFF. Each host port 110A-110F is allocated 128K of logical memory space. With the previously indicated address space being reserved, in host interface 12 there may be a maximum of 128 host ports on the embodiment disclosed.

Provided below in Table A is the summary of potential address allocations for a representative number of the host ports.

TABLE A ______________________________________ HOST PORT 0 E0000000 TO E001FFFF HOST PORT 1 E0020000 TO E003FFFF HOST PORT 2 E0040000 TO E005FFFF . . . . . . . . . HOST PORT 127 E0FE0000 TO E0FFFFFF ______________________________________

The addressing scheme suggested in Table A allows communication between the host computer and the host interface to occur at the port level. That is, there are no special address spaces associated with the functions between the host computer and the various host interface cir