Far end echo cancellation method and apparatus

Claims

What is claimed is:

1. In a full duplex communications apparatus having at least two communicating modem stations, each station having

a transmitter for placing transmit communications signals onto a two wire communications path,

a receiver for receiving received communications signals from said communications path, and

wherein each said received communications signal at a station has a noise-free signal component and a noise signal component, said noise signal component including a far end echo signal generated from said transmit signals of the station,

apparatus for reducing the effect of the far end echo signal at the receiver comprising

quadrature detection and equalization circuitry for generating from a said received signal an I and a Q equalized receiver signal,

receiver decision circuitry responsive to a compensated I and Q equalized receiver signal for generating a receiver decision and for using the receiver decision for generating an I and a Q error update signal,

far end echo compensation circuitry responsive to said I and Q error update signals and a reference signal from the transmitter of the station for generating an I and a Q far end echo cancellation signal,

means for combining said I echo cancellation signal and said I equalized receiver signal for generating said compensated I equalized receiver signal for delivery to said receiver decision circuitry, and

means for combining said Q echo cancellation signal and said Q equalized receiver signal for generating said compensated Q equalized receiver signal for delivery to said receiver decision circuitry.

2. The apparatus of claim 1 wherein said far end echo compensation circuitry comprises

a linear combination circuitry responsive to said I and Q error update signals and said reference signal for generating an I and Q unrotated echo canceler output signal,

a phase locked loop rotation circuit responsive to said I and Q unrotated canceler signals and to a rotation control update signal from the receiver decision circuitry for generating said I and Q far end echo cancellation signals, and

means, at said receiver decision circuitry, responsive to said compensated I and Q equalized signals for computing the rotation control update signal.

3. The apparatus of claim 1 wherein

said I combining means and said Q combining means comprise

an I summation circuitry for generating said compensated I receiver signal equal to a sum of said I cancellation signal and said I equalized receiver signal for delivery to said decision circuitry, and

a Q summation circuitry for generating said compensated Q receiver signal equal to a sum of said Q cancellation signal and said Q equalized receiver signal for delivery to said decision circuitry, and

said detection and equalization circuitry further comprises

a phase locked loop rotation circuitry for generating said I and Q equalized receiver signals from unrotated I and Q error equalized receiver signals in response to a rotation control signal from the receiver decision circuitry.

4. The apparatus of claim 1 further comprising

synchronization and amplitude circuitry for generating said reference signal as an amplitude interpolated signal from said transmitter operating at a first clock rate, and synchronized to said receiver operating at a receiver clock rate different than the first clock rate, said receiver clock rate being synchronized to the received communications signals.

5. The apparatus of claim 4 wherein said synchronization and amplitude interpolation circuitry

receives as its input discrete sample signals output by the transmitter at the baud rate of the transmitter, and

has circuitry for providing said amplitude interpolated reference signal without converting the transmit signal to an analog signal and thereafter resampling a filtered version of the analog signal at the receiver clock rate.

6. The apparatus of claim 4 wherein said synchronization and interpolation circuitry comprises

circuitry responsive to the receiver clock signal for digitally filtering and sampling a transmitter output signal at virtually any desired sampling phase or frequency corresponding to said clock signal for providing a sampled transmitter reference signal at a sample frequency corresponding to said receiver clock rate.

7. The apparatus of claim 6 wherein said synchronization and interpolation circuitry further comprises

means for interpolating between sample outputs of said filtering and sampling circuitry for providing a sampled value of said transmit signal as the reference signal in substantial synchronization with a receiver clock sample signal.

8. The apparatus of claim 7 wherein said filtering and sampling circuitry comprises

filter means having a span of at least twelve transmit baud periods.

9. The apparatus of claim 1 wherein said far end echo compensation circuitry comprises

a linear combination circuitry responsive to rotation compensated I and Q error update signals and said reference signal for generating an I and Q unrotated echo canceler output signal,

a phase locked loop rotation circuit responsive to said I and Q unrotated canceler signals and to a rotation control update signal from the receiver decision circuitry for generating said I and Q far end echo cancellation signals,

an inverse rotation circuitry responsive to the phase locked loop rotation circuit for rotating the I and Q error update signals for providing said rotation compensated error update signals for updating said linear combination circuitry, and

means, at said receiver decision circuitry, responsive to said compensated I and Q equalized signals for computing the rotation control update signal.

10. In a full duplex communications apparatus having at least two communicating modem stations, each station having

a transmitter for placing transmit communications signals onto a two wire communications path,

a receiver for receiving received communications signals from said communications path, and

wherein each said received communications signal at a station has a noise-free signal component and a noise signal component, said noise signal component including a far end echo signal generated from said transmit signals of the station,

apparatus for reducing the effect of the far end echo signal at the receiver comprising

quadrature decision and equalization circuitry for generating from a said received signal an I and a Q equalized receiver signal,

receiver decision circuitry responsive to a compensated I and Q equalized receiver signal for generating a receiver decision and an I and a Q error update signal,

far end echo compensation circuitry for generating an I and a Q far end echo cancellation signal including

a linear combination circuitry responsive to said I and Q error update signals and a reference signal for generating an I and a Q unrotated echo canceler output signal,

a phase locked loop rotation circuit responsive to said I and Q unrotated canceler signals and to a rotation control update signal from the receiver decision circuitry for generating said I and Q far end echo cancellation signals, and

means, at the receiver decision circuitry, responsive to said compensated I and Q equalized signals, said I and Q cancellation signals, and said receiver decision, for computing the rotation control update signal,

an I summation circuitry for generating said compensated I receiver signal equal to a sum of said I cancellation signal and said I equalized receiver signal for delivery to said decision circuitry,

a Q summation circuitry for generating said compensated Q receiver signal equal to a sum of said Q cancellation signal and said Q equalized receiver signal for delivery to said decision circuitry,

a phase locked loop rotation circuitry for generating said I and Q equalized receiver signals from unrotated I and Q equalized receiver signals in response to a rotation control signal from the receiver decision circuitry, and

synchronization circuitry for generating said reference signal from said transmitter operating at a first clock rate and synchronized to said receiver operating at a receiver clock rate different than the first clock rate, said receiver clock rate being synchronized to the received communications signals

said synchronization circuitry including

circuitry responsive to the receiver clock signal for digitally filtering and sampling a transmitter output signal corresponding to said transmit communications signal at a sample frequency corresponding to said receiver clock rate, and

means for interpolating between sample outputs of said filtering and sampling circuitry for providing a sampled value of said transmit signal as the reference signal in substantial synchronization with a receiver clock sample signal.

11. In a full duplex communications apparatus having at least two communicating modem stations, each station having

a transmitter for placing transmit communications signals onto a two wire communications path,

a receiver for receiving received communications signals from said communications path, and

wherein each said received communications signal at a station has a noise-free signal component and a noise signal component, said noise signal component including a far end echo signal generated from said transmit signals of the station,

apparatus for reducing the effect of the far end echo signal at the receiver comprising

quadrature decision and equalization circuitry for generating from a said received signal an I and a Q equalized receiver signal,

receiver decision circuitry responsive to a compensated I and Q equalized receiver signal for generating a receiver decision and an I and a Q error update signal,

far end echo compensation circuitry for generating an I and a Q far end echo cancellation signal including

a linear combination circuitry responsive to rotation compensated I and Q error update signals and a reference signal for generating an I and a Q unrotated echo canceler output signal,

a phase locked loop rotation circuit responsive to said I and Q unrotated canceler signals and to a rotation control update signal from the receiver decision circuitry for generating said I and Q far end echo cancellation signals,

an inverse rotation circuitry responsive to the phase locked loop rotation circuit for rotating the I and Q error update signals for providing said rotation compensated error update signals for updating said linear combination circuitry, and

means, at the receiver decision circuitry, responsive to said compensated I and Q equalized signals, said I and Q cancellation signals, and said receiver decision, for computing the rotation control update signal,

an I summation circuitry for generating said compensated I receiver signal equal to a sum of said I cancellation signal and said I equalized receiver signal for delivery to said decision circuitry,

a Q summation circuitry for generating said compensated Q receiver signal equal to a sum of said Q cancellation signal and said Q equalized receiver signal for delivery to said decision circuitry,

a phase locked loop rotation circuitry for generating said I and Q equalized receiver signals from unrotated I and Q equalized receiver signals in response to a rotation control signal from the receiver decision circuitry, and

synchronization circuitry for generating said reference signal from said transmitter operating at a first clock rate and synchronized to said receiver operating at a receiver clock rate different than the first clock rate, said receiver clock rate being synchronized to the received communications signals

said synchronization circuitry including

circuitry responsive to the receiver clock signal for digitally filtering and sampling a transmitter output signal corresponding to said transmit communications signal at a sample frequency corresponding to said receiver clock rate, and

means for interpolating between sample outputs of said filtering and sampling circuitry for providing a sampled value of said transmit signal as the reference signal in substantial synchronization with a receiver clock sample signal.

12. In a full duplex communications apparatus having at least two communicating modem stations, each station having

a transmitter for placing transmit communications signals onto a two wire communications path,

a receiver for receiving received communications signals from said communications path, and

wherein each said received communications signal at a station has a noise-free signal component and a noise signal component, said noise signal component including a far end echo signal generated from said transmit signals of the station,

a method for reducing the effect of the far end echo signal at the receiver comprising the steps of

quadrature detecting and equalizing the received signals for generating from said received signals and I and a Q equalized receiver signal,

generating a receiver decision from a compensated I and Q equalized receiver signal,

generating an I and a Q error update signal using the receiver decision and the compensated I and Q equalized receiver signal,

generating an I and a Q far end echo cancellation signal in response to said I and Q error update signals and a reference signal from the transmitter of the station,

combining said I echo cancellation signal and said I equalized receiver signal for generating said compensated I equalized receiver signal for delivery to a receiver decision circuitry, and

combining said Q echo cancellation signal and said Q equalized receiver signal for generating said compensated Q equalized receiver signal for delivery to said receiver decision circuitry.

13. The method of claim 12 wherein said far end echo cancellation signal generating step comprises the steps of

linearly combining samples of and said reference signal according to said I error update signal for generating an I linear combination output signal,

linearly combining samples of said reference signal according to said Q error update signal for generating a Q linear combination output signal,

rotating said I and Q linear combination signals in response to a phase error correction signal driving a phase rotation circuit for generating said I and Q far end echo cancellation signals, and

generating the phase error correction for the next baud in response to the compensated I and Q equalized receiver signals, the rotated cancellation signals, and a receiver decision.

14. The method of claim 12 wherein said I combining step and said Q combining step comprise the steps of

generating the sum of said I cancellation signal and said I equalized receiver signal,

generating the sum of said Q cancellation signal and said Q equalized receiver signal, and

generating said I and Q equalized receiver signals, using a phase locked loop rotation circuitry, in response to a rotation control signal from the receiver decision circuitry.

15. The method of claim 12 further comprising the step of

generating said reference signal as an amplitude interpolated signal from said transmitter operating at a first clock rate, and synchronized to said receiver operating at a receiver clock rate different than the first clock rate, said receiver clock rate being synchronized to the received communications signals.

16. The method of claim 15 wherein said interpolated reference signal generating step comprises the step of

digitally filtering and sampling a transmitter output signal at virtually any desired sampling phase or frequency corresponding to said clock signal for providing a sampled transmitter reference signal at a sample frequency corresponding to said receiver clock rate.

17. The method of claim 16 wherein said generating step further comprises the step of

interpolating between sample outputs from said filtering and sampling step for providing a sampled value of said transmit signal in substantial synchronization with said receiver clock signal.

18. The method of claim 17 wherein said filtering and sampling step comprises the step of

providing a filter span extending over at least twelve transmit baud periods.

19. In a full duplex communications apparatus having at least two communicating modem stations, each station having

a transmitter for placing transmit communications signals onto a two wire communications path,

a receiver for receiving received communications signals from said communications path, and

wherein each said received communications signal at a station has a noise-free signal component and a noise signal component, said noise signal component including a far end echo signal generated from said transmit signals of the station,

a method for reducing the effect of the far end echo signal at the receiver comprising the steps of

quadrature detecting and equalizing the received signals for generating from said received signals an I and a Q equalized receiver signal,

generating a receiver decision and an I and a Q error update signal from a compensated I and Q equalized receiver signal,

linearly combining samples of said reference signal according to said I error update signal for generating an I linear combination output signal,

linearly combining samples of said reference signal according to said Q error update signal for generating a Q linear combination output signal,

rotating said I and Q linear combination signals in response to a phase error correction signal from a receiver decision step for generating said I and Q far end echo cancellation signals,

generating said phase error correction for the next baud in response to the compensated I and Q equalized receiver signals, the rotated cancellation signals, and a receiver decision,

generating the sum of said I cancellation signal and said I equalized receiver signal,

generating the sum of said Q cancellation signal and said Q equalized receiver signal,

generating said I and Q equalized receiver signals, using a phase locked loop rotation circuitry, in response to a rotation control signal from said receiver decision step, and

generating said reference signal from said transmitter operating at a first clock rate, and synchronized to said receiver operating at a receiver clock rate different than the first clock rate, said receiver clock rate being synchronized to the received communications signals, said reference signal generating step comprises the step of

digitally filtering and sampling a transmitter output signal at a varying sampling phase and frequency corresponding to said clock signals for providing a sampled transmitter reference signal at a sample frequency corresponding to said receiver clock rate, and

interpolating between sample outputs from said filtering and sampling step for providing a sampled value of said transmit signal in substantial synchronization with said receiver clock signal.

BACKGROUND OF THE INVENTION

The invention relates generally to communications systems and methods and, in particular, to a method and apparatus for canceling far end echo in a full duplex modem communications system.

A typical modem communications system has a plurality of stations, each of the stations having a modem. The modem has separate transmitting and receiving sections. Each modem is typically a two wire unit and, when the two wire connection reaches the telephone switching office, the signals are converted to a four wire system. The connection from the modem connected two-wire to the telephone switching office four-wire system is designated a near end connection while the connection from the switching system back to the two-wire path connecting to the remote modem is designated a far end connection. It is well known that there results, from the two-to-four and four-to-two wire conversions, a noise in the form of echoes which travel along the communication path and which distorts, and thereby causes errors to occur in, the signal reception process.

It is further well known that the echo resulting from the modem near end boundary as a result of a signal transmitted by the transmitter, the received near end echo, is, to a very good approximation, a linear function of the transmitted signal and is combined additively by the telephone line with the desired signal coming from the other modem to form a "composite" received signal. This echo is not affected by and does not exhibit frequency translation or phase jitter. Thus the received near end echo can be eliminated by linearly and adaptively filtering the transmitted signal and subtracting that adaptive filter output from the composite signal.

The echo returning from the far end boundary, as a result of a transmission by the transmitter of the modem, also distorts the signal received at the modem from a remote transmitter source. The received far end echo, however, is subject to both frequency and phase variations. And, while the far end echo received by a receiver is usually a small signal relative to the desired received signal, it nevertheless is often large enough that reliable reception is impossible if the far end echo signal is not canceled. When the far end echo is affected by frequency or phase variations, it is difficult to adjust a conventional echo canceler with sufficient speed and accuracy to effectively cancel the far end echo.

The conventional approach to canceling the far end echo contemplates subtracting an echo cancellation signal from the signal received from the two wire telephone line to produce a corrected, hopefully echo-free, receiver signal which is then processed by the receiver. The corrected signal is typically also employed by the feedback loop as an error update signal to adjust an adaptive linear filter which produces the cancellation signal from delayed samples of the transmit signal. The feedback loop error update signal, however, has a large "real receiver" signal and a relatively small echo signal. The relatively large "real receiver" signal to a large extent masks the desired error signal, that is, the remaining far end echo present on the line. As a result, adaptation of the echo canceler may not be sufficiently fast or accurate to track changes resulting from frequency translation and other phenomena.

To improve the echo cancellation signal generation process, various references use transversal filtering methods including signal rotation in connection with quadrature detection and equalization. The references also describe using the output of the decision threshold circuitry for controlling the transversal filtering process in generating the echo cancellation signal. Even so, however, the result of the echo cancellation circuitry has not been satisfactory.

An object of the invention is therefore an improved far end echo cancellation method and apparatus. Further objects of the invention are a method and apparatus for providing a representation of the transmitter output signal of a full duplex modem synchronized to the receiver's timing reference for use in canceling the far end echo signal mixed with the true receiver input signal. Other objects of the invention are a method and apparatus for effecting synchronization of the transmitter output samples to the receiver samples (even when neither modem is in loop-back timing), and for providing such synchronization without using an analog interpolation filter, and for employing threshold decision outputs from a receiver decision circuitry for controlling the phase and amplitude of a far end echo cancellation signal.

SUMMARY OF THE INVENTION

The invention relates generally to a full duplex communication apparatus having at least two communicating modem stations. Each station has a transmitter for placing transmitted communications signals onto a two-wire communications path and a receiver for receiving received communications signals from the communications path. The received communications signal at the station has noise-free signal component and a noise signal component. The noise signal component includes a far end echo signal generated and correlated to the transmit signals of the station. The apparatus reduces and preferably cancels the effect of the far end echo signal at the receiver.

The apparatus features a quadrature detection and equalization circuitry for generating from the received signals an I and a Q equalized receiver signal; receiver decision circuitry responsive to a compensated I and Q equalized receiver signal for generating a receiver decision and for generating an I and a Q error update signal; a far end echo compensation circuitry responsive to the I and Q error update signals and to a reference signal from the transmitter of the station for generating an I and a Q far end echo cancellation signal; and circuitry for combining the I and Q echo cancellation signals with the I and Q equalized receiver signals for generating the compensated I and Q equalized receiver signals for delivery to the receiver decision circuitry. Preferably, the far end echo compensation circuitry includes a far end echo cancellation phase locked loop rotation element that rotates, in response to the compensated I and Q equalized receiver signals and a receiver decision, echo canceler I and Q signals to compensate for frequency translation in the far end echo signals.

In particular embodiments of the invention, the apparatus further features synchronization circuitry for generating the reference signal from transmitter signals generated at a transmitter clock rate, and providing a reference signal synchronized to the receiver operating at a receiver clock rate different than the transmitter clock rate. The receiver clock rate is synchronized to the received communications signals.

In a particular aspect, the synchronization circuitry features circuitry responsive to the receiver clock signal for digitally filtering a version of the transmitter signal synchronized to the transmitter clock rate and producing a version of the transmitter signal synchronized to the receiver clock rate. In this aspect, the apparatus provides circuitry for adjustably interpolating between samples of the transmit signal for generating the reference signal for the far end echo compensation circuitry. This procedure produces a reference signal in substantial synchronization to the receiver clock sample signal and also allows for transmitting signal samples synchronized to the received signal samples even when the transmitter clock rate is not synchronized to the receiver baud rate.

In another aspect of the invention, a method for reducing the effect of far end echo signals at the receiver features the steps of quadrature detecting and equalizing the received signals for generating from the received signals an I and a Q equalized receiver signal; generating a receiver decision and an I and a Q error update signal from compensated I and Q equalized receiver signals; generating an I and a Q far end echo cancellation signal in response to the I and Q error update signals and a reference signal generated from the transmitter output of the station; combining the I and Q echo cancellation signals and the I and Q equalized receiver signal for generating, respectively, the compensated I and Q equalized receiver signals for delivery to the receiver decision circuitry.

In other aspects, the method further features generating the reference signal from the transmitter operating at a first clock rate, the reference signal being synchronized to the receiver operating at a receiver clock rate which is different than the first clock rate of the transmitter. The receiver clock rate is synchronized to the received communications signals. The reference signal generating step further features digitally filtering and upsampling a transmitter output signal corresponding to the transmit communications signals, at virtually any desired sampling phase or frequency corresponding to the clock signals, and in particular at a sample frequency corresponding to the receive clock rate. In this aspect, the generating step further features the step of interpolating between sample outputs resulting from the filtering and upsampling step for providing a sampled output value of the transmit signal which is in substantial synchronization with the receiver clock signal.

In yet another aspect of the invention, an apparatus generates, in the digital domain, a transmit sample signal in synchronism with a received signal clock. This occurs in a communications system having at least two communicating modem stations. Each modem station has a transmitter for placing transmit communications signals onto a communications path at a transmitter baud rate and a receiver for receiving received communications signals from the communications path at a baud rate different than the transmitter baud rate. The apparatus features digital synchronization circuitry which receives as its input digital data signals from the transmitter at a clock rate derived from the baud rate of the transmitter and which provides a synchronized reference signal to the receiver at the received signal baud rate.

In other aspects of the invention, the synchronization circuitry features circuitry for digitally filtering and upsampling the digital data to a sample frequency substantially greater than the received signal clock and circuitry for interpolating between sample outputs of the filtering and upsampling circuitry for providing a sampled value of the digital data signals as the reference signal in synchronization with the received signal baud rate.

In another aspect, the method of the invention for generating a transmit sample signal, in the digital domain and in synchronism with the received signal, includes the step of digitally generating the transmit sample signal from transmitter signal data available at a clock rate derived from the transmitter baud rate and synchronizing the transmit sample signal to the received signal clock. In particular aspects of the method of the invention, there are featured the steps of digitally filtering and upsampling the transmitter sample signal to a sample frequency substantially greater than the received signal clock and interpolating between sample outputs of the filtering and upsampling step to provide a sampled value of the digital data signals in synchronism to the received signal baud rate.

BRIEF DESCRIPTION OF THE DRAWINGS

Other objects, features, and advantages of the invention will be apparent from the following description taken together with the drawings in which:

FIG. 1 is a general block diagram of a two station full duplex modem communication system;

FIG. 2 is a simplified block diagram of a typical error compensation method according to prior art methods;

FIG. 2A is a vector diagram illustrating the components of a signal input to the decision circuitry;

FIG. 2B is a vector diagram illustrating the method for determining the far end echo cancellation signal vector correction from the decision input signal and the receiver decision vector;

FIG. 2C is a vector diagram illustrating the method for determining the far end echo rotation update signal;

FIG. 3 is a schematic block diagram of a particular embodiment of the invention illustrating the generation and application of far end echo cancellation signals to a quadrature component receiver system;

FIG. 4 is a schematic block diagram of one particular apparatus for generating the reference signal employed by the far end echo cancellation circuitry;

FIG. 4A is a schematic block diagram of a preferred analog implementation of apparatus for generating the reference signal employed by the far end echo cancellation circuitry;

FIG. 5 is a schematic representation of an apparatus for generating the reference signal of FIG. 4 solely in the digital domain;

FIG. 6 is a typical finite impulse response (FIR) filter for upsampling the input signal at the baud rate to a sampled signal having a greater sampling rate;

FIG. 7 illustrates an alternate implementation of the filter of FIG. 6;

FIG. 8 illustrates the convolution of the filter of FIG. 7 with a digital low pass filter in accordance with a preferred embodiment of the invention;

FIG. 9 is a schematic representation of an apparatus employing two digital filters for producing an interpolated sample output reference signal;

FIG. 10 is a schematic representation of an apparatus employing a combined filter and interpolation circuitry for producing an interpolated sample output reference signal; and

FIG. 11 is a schematic representation of the combined filter and interpolation circuitry in a complete data communications system.

DESCRIPTION OF PARTICULAR PREFERRED EMBODIMENTS

Referring to FIG. 1, a communications system and network 8 has a plurality of modem stations including an illustrated local transmitter/receiver modem combination 10, and a remote transmitter/receiver modem combination 12. Each modem has separate receiving and transmitting circuitries, Rx and Tx, respectively. The modems are two-wire units. When the two-wire connection reaches a telephone switching office 13, the two-wire system signals are converted to a four-wire system. The telephone office connection is illustrated by a boundary 14 for the connection from modem 10 to the telephone switching office, a so-called near end connection for modem 10, and a boundary 16, a so-called far end connection for modem 10. As a result of the two-to-four and four-to-two wire conversions, a transmitted signal from the transmitter of modem 10 produces noise in the form of echoes 17 and 19 at each of connection boundaries 14 and 16 respectively. The echo resulting from the near end boundary 14, as a result of a signal transmitted by the transmitter of modem 10, is a near end echo 17 which has no frequency or phase translation. The near end echo corrupts the signal received by the receiver of modem 10 from, for example, the transmitter of modem 12. The near end echo 17 received at modem 10 is a linear function of the signal transmitted by the modem 10 and can be eliminated using a finite impulse response (FIR) filter.

The echo 19, returning from the far end boundary 16, as a result of a transmission from the transmitter of modem 10, also adds to and distorts the signal received at modem 10 from the transmitter of modem 12, but, unlike the near end echo, is subject to both frequency and phase variations. The far end echo 19 also has a small signal energy relative to that of the received signal.

In a previous solution to the far end echo cancellation problem, referring to FIG. 2, the received signal over a line 20 (which signal includes the far end echo), is added or summed with an echo cancellation signal over a line 22 in an adder circuitry 23 to produce a resulting corrected received signal over a line 24. That corrected signal is converted to a digital signal in an analog-to-digital (A/D) converter 26 for processing by a receiver circuitry 28. The signal over line 24 is also employed, typically, to update the coefficients of an adaptive filter 32 which generates, from a reference signal, the echo cancellation signal over line 22.

The corrected received signal over line 24, however, has a large "real receiver" signal (corresponding to the signal from the remote transmitter) and a relatively small error signal. The relatively large receiver signal, to a large extent, masks the true error signal, that is, the remaining far end echo noise present on the line 24. As a result, the cancellation of the far end echo signal is not satisfactory when fast, accurate adaptation is required. Performance would be substantially improved if the real receiver signal could be removed so that only the noise error signal were employed in connection with the feedback system. It is this goal to which the present invention is directed.

In a typical transmission and receiving system which uses, for example, quadrature detection, each signal is represented in a two-dimensional space having, as is well known in the art, Q and I components. A typical receiver estimates, for a received signal having component values Q' and I', the location of the nearest true receiver signal. ("Nearest" in this context need not be nearest in distance, depending upon the particular estimation and detection method