An approach to rapidly pre-charging bit lines (104a and 104b) after a write operation to a memory cell (128) is disclosed. Following a write operation, a Y-select signal (Yj) and its inverse (/Yj) are maintained in an active state for a given period of time, keeping the transistors within a column selecting circuit (102) turned on. Pre-charging circuits (106 and 108) are also turned on. Consequently, the bit lines (104a and 104b) are pre-charged by the bit line pre-charging circuit (106), and by the pre-charging circuit (108) by way of a read bus (124) and the column selecting circuit (102). Furthermore, a write amplifier (112) is also activated, resulting in the bit lines (104a and 104b) being further pre-charged by way of a write bus (126) and the column selecting circuit (102).

An improved DRAM is disclosed, in which a number of sense amplifiers to be activated simultaneously can be selected by using a bonding option method. An output signal /.o slashed..sub.A supplied from a bonding option circuit 11 is applied to column interlock releasing circuit 7. When an operation mode in which the number of the sense amplifiers to be activated simultaneously is large is selected, a column interlock releasing signal /.o slashed. is delayed, and enabling of a column decoder 3 is delayed. In the operation mode, in which the number of the sense amplifiers to be activated simultaneously is large, the enabling of the column decoder 3 is delayed, and a conducting timing of an IO gate circuit 16 is delayed. A sense amplifier 15 can sufficiently amplify a potential difference between bit lines, so that an error in the data reading operation is prevented.

The invention's reference precharge circuit and bit line precharge circuits are comprised of two NFET transistors and one PFET transistor. In the preferred embodiment of the invention where the supply voltage is 3.0 volts, the two NFET transistors result in a voltage drop of 2.0 volts so as to produce a reference precharge signal or a bit line precharge signal having a voltage of 1.0 volts. When a precharge enable signal is on, the PFET transistor is connected to ground and is barely on such that the path from the reference precharge signal or the bit line precharge signal to ground is a low impedance path. Moreover, the path from the reference precharge signal or the bit line precharge signal to the supply voltage is also of low impedance. Accordingly, the voltages present at the reference precharge signal or the bit line precharge signal are substantially noise free. The invention also utilizes a unique sense amp that quickly detects changes in the voltage level of a bit line in relation to the voltage level of the reference precharge signal. The sense amp uses an NFET transistor driven by the reference precharge signal which causes the NFET transistor to barely conduct current. This results in dramatically increasing the reaction time of the invention's sense amp. Moreover, because the invention utilizes low bit line and reference precharge voltages, the invention's sense amp is very sensitive to small changes in the bit line voltage relative to the reference precharge voltage.

An improved DRAM is disclosed, in which a number of sense amplifiers to be activated simultaneously can be selected by using a bonding option method. An output signal /.phi..sub.A supplied from a bonding option circuit 11 is applied to column interlock releasing circuit 7. When an operation mode in which the number of the sense amplifiers to be activated simultaneously is large is selected, a column interlock releasing signal /.phi. is delayed, and enabling of a column decoder 3 is delayed. In the operation mode, in which the number of the sense amplifiers to be activated simultaneously is large, the enabling of the column decoder 3 is delayed, and a conducting timing of an IO gate circuit 16 is delayed. A sense amplifier 15 can sufficiently amplify a potential difference between bit lines, so that an error in the data reading operation is prevented.

An ECL-to-CMOS buffer having a single-sided delay comprises an ECL logic gate, a level converter, a plurality of series connected inverters, and a NOR gate. The ECL logic gate receives an ECL level input signal, and provides complementary intermediate level logic signals. The level converter receives the intermediate level logic signals and provides a CMOS level output signal. The NOR gate receives the CMOS level output signal, via the series connected inverters, at an input terminal after a predetermined delay. One of the intermediate level logic signals is also received by the NOR gate at a second input terminal. The CMOS level output signal is delayed for a predetermined time in a low-to-high transition, with no unwanted delay in a high-to-low transition.