In a data processing system, a data processing unit contains data processing logic including shadowed functional registers for storing the data being processed. The units also include fault monitoring logic, including, for each shadowed functional register, a shadowing copy register connected in parallel from the corresponding shadowed register to receive and store a copy of the data resident in the shadowed register. Test logic is connected from the shadowed and shadowing registers for comparing the data resident in the shadowed and shadowing registers and providing indications of possible faults in the data processing logic. The shadowed and shadowing registers are connected in a serial scan chain through a serial scan data path. The integrity of the fault monitoring logic is tested by serially shifting, or scanning, known test patterns of bits through the serial scan chain comprised of the shadowed registers and shadowing registers. A first set of patterns are selected so that the test patterns themselves should not induce any errors to appear to the comparison logic so long as the the test logic is correct, so that any errors that are detected are due to a fault in the test logic. A second set of test patterns are selected to induce errors to appear as the patterns are shifted, bit by bit, through the scan chain. The first patterns thereby determine that there are not errors in the fault monitoring logic itself, and the second patterns that the fault monitoring logic is detecting errors correctly.

An apparatus for and method of providing rapid communication between separately clocked system elements. A network interface module is used as the overall system control and communication interface to each of the separate system elements. Each of these system elements is controlled by a different and dedicated programmable micro-engine. A separate register located within and addressable by each of the micro-engines provides the basic data transfer path. Access by a micro-engine to the corresponding register is easily accomplished by firmware. The bit serial scan interface between the network interface module and each of the registers is controlled by the network interface module.

A technique for saving data related to given machine events in a control that normally records machine events or faults in a first-in, first-out buffer of finite size called an occurrence log by selectively setting the control to respond to the occurrence of a given machine fault or event, monitoring the operation of the machine for the occurrence of the given machine event, and initiating the transfer of the data in the buffer to a nonvolatile memory. Also included is the technique of delaying the transfer of the data in the buffer memory to the non-volatile memory until the recording of a given set number of events is determined in the buffer.

The hierarchical distributed knowledge based system functions in a machine initiated maintenance environment to provide efficient and timely maintenance of customer equipment. The hierarchical, distributed knowledge based system provides the failure evaluation function through the use of an expert or knowledge based system that is installed in the customer equipment. The knowledge based system makes use of a set of rules and hypotheses to operate on data collected from various points within the customer equipment to monitor the operational integrity of the customer equipment. This knowledge based system identifies the occurrence of a failure within the customer equipment and functions using its rules, hypotheses and collected data to isolate the source of the error in the customer equipment and, whenever possible, "fence" or isolate the failed field replaceable unit that has caused the error. A significant additional attribute of this system is the provision of at least one more level of knowledge based system to provide a more global failure evaluation capability.

In a data processing system including a bus connected to a plurality of devices capable of driving said bus, error reporting and isolation is achieved by signaling a self-check to each device connected to the bus to determine if it was driving the bus at the time an error occurred. The bus check request is generated by one of the devices connected to the bus in response to detecting either a parity error or an internal error. If a parity error is detected, a bus check request is signaled to a combining unit connected to the bus. The combining unit signals the self-check to each of the devices attached to the bus in response to receiving the bus check request. Each device determines whether it was driving the bus at the time the error occurred and, if so, sets a source of error indicator on the device. Similarly, if an internal error is detected, the detecting device sets source of error and internal error indicators on the detecting device and signals a bus check request to the combining unit. The source of error and internal error indicators are accessible to a machine check or service processor mechanism in the data processing system.