An efficient method of generating test sequences for sequential circuits is disclosed. This method generates a test sequence for a combinational circuit which includes an object fault, examines memory elements where a resulting state (other than "don't care") has been set as a result of the fault. This is followed by fault propagation and state justification. In the event that, due to such factors as limitations in computing time, generation of test sequence was aborted during fault propagation or state justification, the states of the memory elements are provided for determining which memory element should be scanned to detect the fault. In another embodiment an assumed fault from previous processing has been propagated to a memory element and, thus, to a pseudo primary input terminal. The results of the previous processing are used to propagate the fault to a primary output terminal or to another memory element and, thus, to another pseudo primary output terminal. Other embodiments of the invention generate tests according to degrees of difficulty in generating a fault of a particular type along various signal paths in the circuit. These include faults propagated to the control input terminals of memory elements. A final embodiment of the invention determines, as a result of prior processing, values which should be set for a tree circuit input in order to set the tree circuit output to a 0 or a 1. Then, during test generation, when selecting the signal line and the signal to be set, the tree data is used to expedite the selection and processing of signal line and value assignments.

Disclosed is a method and apparatus for generating a test sequence to test a fault in a digital circuit. According to this method and apparatus, when a fault propagation process for a fault, for which a test sequence is generated is not successful, at least a segment of a path to propagate the effects of the fault is memorized as illegal information., And the fault propagation process is restarted for the same fault without selecting the illegal information. Hence, the chance of a successful fault propagation process is increased, which leads to the improvement of the fault coverage. In addition, according to the apparatus and method, it is detected whether a state transition goes into a loop (i.e., two identical states exist) in the state initialization process and then the process is restarted by defining the state caused the loop as an illegal state. Hence, the chance of a successful state initialization process is increased, which leads to the improvement of the fault coverage.

A method based on continuous optimization techniques for generating test vectors for use in testing VLSI circuits includes representing digital circuits as smooth functions. The test generation problem is formulated as the minimization of the objective function over a hypercube in Euclidean space. The dimension of the space is equal to the number of primary inputs of the circuit. The smooth function is optimized inside a convex polytope using a variant of gradient descent and line search strategies. The solution starts at the center of the hypercube and follows a trajectory to one of the corners of the hypercube that corresponds to a test vector. Once the test vector is determined by this method, electrical signals corresponding to the test vector are applied to the inputs of the VLSI circuits. The outputs of the VLSI circuit are monitored in order to locate defects in the circuit. The representation of the logic gates as a continuous family of functions enables the method to quickly find an optimal solution to the test generation problem.

A system and method for generating a fault model for a logic circuit includes a data storage device for storing information relative to fault models or primitive elements in a logic circuit and for storing fault models for each level of design in a hierarchical logic circuit, a processor for processing the stored information relative to primitives and lower level fault models in the hierarchy for generating fault models for each succeeding higher level of design in the hierarchy, an input device for operator input of information to modify primitive fault models and a display subsystem for displaying various aspects of the hierarchical fault model generated in accordance with the present invention.

A method for generating and simulating test patterns to detect faults (57, 63) in an integrated circuit. The method comprises identifying all nets (27) which can potentially be shorted together. Each potential fault (34, 36, 37, 38, 39) is categorized as either a feedback fault or a non-feedback fault. A test pattern is generated to detect the selected potential fault. The test pattern is simulated to determine which additional potential faults are detected by the test pattern. Potential faults which are detected by the test pattern are deleted from the fault list (12). The method is repeated until no potential faults remain on the fault list (12).