High speed silicon-on-insulator radiation hardened semiconductor devices and a method of fabricating same. Starting with a SIMOX wafer (10) having a layer of silicon (12) on a layer of buried oxide (11), P-well and N-well masks are aligned to an oversized polysilicon mask (16). This produces relatively thick source and drain regions (18) and relatively thin gate regions (17). The relatively thick source and drain regions (18) educe the risk of dry contact etch problems. N-channel and P-channel threshold voltages are adjusted prior to the formation of active areas, thus substantially eliminating edge and back channel leakage. A sacrificial thin oxide layer (21) is employed in fabricating the N-well and P-well implants so that both front and back channel threshold voltage adjustments are controlled. Good control of doping profiles is obtained, leading to excellent threshold voltage control and low edge and back channel leakages. The speed of devices fabricated using the method of the present invention is high due to reduced capacitances resulting from thinner silicon-on-insulator films. The present invention is fabricated using present equipment and available technology, and provides an easy, straight forward and cost-effective process to fabricate very high speed CMOS devices which are latch-up free and radiation hardened.

A method of fabricating a thin film transistor includes the steps of forming an active layer on an insulating substrate; forming an insulating layer and a first metal layer on the active layer; forming a photoresist pattern for forming a gate electrode on the metal layer; etching the metal layer and the insulating layer by using the photoresist pattern as a mask, and respectively forming a gate electrode and a gate insulating layer to expose a part of the active layer; forming an amorphous silicon layer on the resultant whole surface of the substrate; forming a second metal layer on the amorphous silicon layer; patterning the second metal layer and the amorphous silicon layer by a photolithographic process to form an offset layer and a source/drain electrode; and carrying out a lift-off process to remove the photoresist pattern, and exposing the surface on the gate electrode.

A process and structure for improving the conductive capacity of a polycrystalline silicon (poly) structure, such as a bit line. The inventive process allows for the formation of a refractory metal silicide layer on the top and sidewalls of a poly structure, thereby increasing the conductive capacity. To form the titanium silicide layer over the poly feature, the refractory metal is sputtered on the poly, which reacts to form the refractory metal silicide. A second embodiment is described whereby an isotropic etch of the poly feature slopes the sidewalls; then, the refractory metal is sputtered onto the polycrystalline silicon. This allows for the formation of a thicker layer of refractory metal silicide on the sidewalls, thereby further increasing the conductive capacitance of the poly structure. Suggested refractory metals include titanium, cobalt, tungsten, and tantalum.

A method of fabricating a thin film transistor includes the steps of forming an active layer on an insulating substrate; forming an insulating layer and a first metal layer on the active layer; forming a photoresist pattern for forming a gate electrode on the metal layer; etching the metal layer and the insulating layer by using the photoresist pattern as a mask, and respectively forming a gate electrode and a gate insulating layer to expose a part of the active layer; forming an amorphous silicon layer on the resultant whole surface substrate; forming a second metal layer on the amorphous silicon layer; patterning the second metal layer and the amorphous silicon layer by a photolithographic process to form an offset layer and a source/drain electrode; and carrying out a lift-off process to remove the photoresist pattern, and exposing the surface on the gate electrode.