Thermal CVD/PECVD reactor and use for thermal chemical vapor deposition of silicon dioxide and in-situ multi-step planarized process

What is claimed is:

1. A semiconductor processing reactor comprising:

a housing defining a vacuum chamber for mounting a wafer horizontally and including a horizontal, inlet gas manifold over the wafer mounting position for supplying reactant gases to a wafer at the mounting position;

a gas distributor plate mounted peripherally about the wafer mounting position within the chamber, the plate including a circular array of exhaust holes therein;

a vacuum exhaust pump means; and

a circular channel beneath and communicating with the hole array and having an exhaust port connected to the vacuum exhaust pump means for flowing said gases radially across the wafer through the exhaust port, the channel volume providing high conductance relative to said exhaust holes sufficient to enable controlled radial gas flow across the wafer and through said exhaust holes into the channel.

2. A semiconductor processing reactor comprising:

a housing defining a chamber therein for mounting a wafer horizontally;

vacuum exhaust pumping means communicating with the chamber;

a horizontal inlet gas manifold oriented horizontally over the wafer mounting position for supplying reactant gases to a wafer at the mounting position; the manifold also comprising a first central array of holes for dispensing the reactant gas downward to the wafer and a second peripheral array of holes for directing purging gas downward to the periphery of the wafer, the first and second arrays of holes each comprising a number of generally concentric rings with the first central array having random within-ring hole spacing for limiting the number of radially aligned holes and the second peripheral array having a radially staggered pattern to ensure no ring-to-ring radial alignment of holes.

3. The reactor of claim 2, the manifold further comprising an internal plate for directing internal flow radially inwardly across the first, central array of holes.

4. The reactor of claim 2, including means for circulating cooling fluid within the manifold for maintaining the internal surfaces within a selected temperature range and for maintaining the external wafer-adjacent surface above a selected temperature range.

5. A semiconductor processing reactor adapted for single step and in-situ multiple step processing sequences selected from thermal chemical vapor deposition, plasma-enhanced chemical vapor deposition, plasma-assisted etchback, plasma self-cleaning and topography modification by sputtering with uniform wafer processing over a wide range of high pressures .ltoreq. one atmosphere, comprising:

a housing defining a chamber for mounting a wafer for processing at a selected position therein;

a first gas inlet manifold positioned above the selected position, the manifold having a center gas outlet region adapted for directing reactant gases downwardly to a wafer at the selected position and an outer peripheral region adapted for directing purging gas toward the wafer periphery;

a second gas inlet manifold located at the bottom of the chamber and adapted for directing purging gas upwardly and across the wafer;

means for circulating fluid at a controlled temperature within the first gas inlet manifold for maintaining the internal surfaces within a selected temperature range for preventing condensation, decomposition and reaction of said gases therein and for maintaining the external wafer adjacent surface above a selected temperature range for suppressing unwanted deposition thereon;

a radial gas flow pumping means comprising vacuum exhaust pump means gas; a distributor plate mounted peripherally about the wafer mounting position within the chamber, the plate including a circular array of exhaust holes therein; a circular channel formed in the housing communicating with the exhaust holes and having an exhaust port connected to the vacuum exhaust pump means for flowing said deposition gases radially across the wafer and through the exhaust port, said channel volume providing conductance sufficient to enable controlled radial gas flow across the wafer to the exhaust holes;

a thin high emissivity susceptor;

movable susceptor support means mounting the susceptor in a horizontal orientation and adapted for moving vertically for selectively positioning the susceptor and a wafer positioned thereon parallel to the gas manifold at selected positions closely adjacent the gas manifold;

a transparent window forming the bottom of the chamber; radiant heating means mounted to the housing beneath the window comprising lamps and a circular reflector module mounting the lamps in a circular array for directing a collimated beam of radiant energy through the transparent window onto the susceptor with an incident power density substantially higher at the edge of the susceptor than at the center thereof; and

a gas feed-through device connected to the first gas inlet manifold, comprising tube means having inlet and outlet ends and being adapted for providing coaxial flow of deposition gas on the inside thereof and purge gas on the outside thereof into the first manifold, the tube means being adapted for connection to ground at an inlet end and to an RF power supply at the outlet or manifold end for applying RF power to the gas inlet manifold, and the tube means also having a controlled electrical impedance along its length for establishing a constant voltage gradient along said length to prevent breakdown of the gas therein.

6. A semiconductor processing reactor comprising:

a housing defining a chamber therein adapted for the gas chemistry processing of a wafer within the chamber;

a transparent window forming the bottom of the chamber; and

a thin, high emissivity susceptor positioned within the chamber for supporting a wafer; the housing further comprising:

radiant heating means mounted to the housing beneath the window, comprising: a circular array of lamps and a reflector module having an annular reflecting channel therein aligned with the periphery of the susceptor, the reflector module mounting the lamps in a general vertical orientation in a circular array within the channel for directing a substantially collimated beam of radiant energy from the lamps through the transparent window onto the susceptor with an incident power density substantially higher at the edge of the susceptor than at the center thereof.

7. The reactor of claim 6, the radiant energy supplied by the lamps being concentrated substantially in the wavelength range of about 0.7 to 2.5 microns.

8. The reactor of claim 7, the radiant energy supplied by the lamps being concentrated at a peak emission wavelength of approximately 0.9 to 1.5 microns.

9. The reactor of claim 9, wherein the susceptor is selected from graphite, aluminum, ceramic and composites thereof.

10. The reactor of claim 9, the reactor being adapted for operation at pressure of .sup..ltoreq. 760 torr.

11. A semiconductor processing reactor comprising:

a housing defining a chamber therein adapted for the gas chemistry processing of a wafer within the chamber; said housing further including:

a first gas inlet manifold positioned above the wafer and a second gas inlet manifold located at the bottom of the chamber, the first manifold having a center region adapted for directing deposition gas downwardly to the wafer and an outer peripheral region adapted for directing purging gas downwardly to the wafer periphery, and the second manifold being adapted for directing purging gas upwardly to the wafer periphery; and

means for exhausting undeposited gases radially away from the wafer.

12. The reactor of claim 11, adapted for operation at a pressure of 0.1 to 200 torr.

13. The reactor of claim 10 or 11, the first gas inlet manifold having temperature controlled inner and outer surfaces for enhancing control of deposition within the chamber and preventing deposition within the manifold.

14. A chemical vapor deposition reactor, comprising:

a housing defining a chamber therein and being adapted for the chemical vapor deposition of a layer on a wafer within the chamber, and including a gas inlet manifold for supplying deposition gases to the chamber and an RF power supply and matching for forming a deposition gas plasma within the chamber to deposit the layer on the wafer; and

the housing further including a combined RF/gas feed-through device connected to the gas inlet manifold and comprising: tube means having inlet and outlet ends and being adapted for providing co-axial flow of deposition gas on the inside thereof and purge gas on the outside thereof into the gas inlet manifold, the tube means being adapted for connection to ground at the inlet end and to an RF power supply at the outlet or manifold end, and the tube means also having a controlled electrical impedance along its length for establishing a constant voltage gradient along said length to prevent breakdown of the gas.

15. The chemical vapor deposition reactor of claim 14, the gas inlet manifold having temperature controlled inner and outer surfaces suppressing unwanted deposition on the outer surfaces and preventing condensation and deposition within the manifold.

16. The chemical vapor deposition reactor of claim 14, said gas inlet manifold having an inner region adapted for directing deposition gas downwardly to the wafer and an outer peripheral region adapted for directing purging gas downwardly to the wafer periphery; said reactor further including:

a second gas manifold for directing purging gas upwardly to the wafer periphery; and

means for exhausting purging and undeposited deposition gases radially away from said wafer periphery.

17. The chemical vapor deposition reactor of claim 14, 15 or 16:

a transparent window forming the bottom of the chamber;

a thin, high emissivity susceptor positioned within the chamber for supporting a wafer;

radiant heating means mounted to the housing beneath the window, comprising: a circular array of lamps and a reflector module having an annular reflecting channel therein aligned with the periphery of the susceptor, the reflector module mounting said lamps in a general vertical orientation in a circular array within the channel for directing a substantially collimated beam of radiant energy from the lamps through the transparent window onto the susceptor with an incident power density substantially higher at the edge of the susceptor than at the center thereof; and

means for internally cooling the reflector module.

18. A semiconductor processing reactor comprising a housing defining a vacuum chamber therein adapted for the chemical vapor deposition of a layer on a wafer positioned within the chamber, the housing having a closable opening therein for receiving a wafer-holder blade to insert a wafer into the chamber and remove the wafer from the chamber; the housing further comprising:

a first, vertically movable, generally circular horizontal array of fingers adapted for holding the wafer;

a second, vertically movable, generally circular horizontal array of fingers interdigitated with the first fingers, the second fingers being adapted for holding a thin generally circular susceptor in a horizontal orientation;

a first vertically movable elevator mechanism mounting the first fingers and for moving the first fingers (a) upwardly to lift the wafer off the blade preparatory to lifting movement of the second fingers into a processing position and (b) downwardly to return the wafer to the blade; and

a second, vertically movable elevator mechanism mounting the second fingers for moving the second fingers (c) upwardly past the first fingers to lift the wafer therefrom and onto the susceptor and into the said processing position, and (d) downwardly for depositing the processed wafer onto the first fingers preparatory to return by the first fingers to the blade.

19. A chemical vapor deposition reactor system comprising:

a housing forming a vacuum chamber, said housing having a first horizontal gas manifold adapted for introducing reaction gas into the chamber;

a first, vertically movable elevator mechanism;

a first, vertically movable, generally circular horizontal array of fingers adapted for holding a wafer;

a second, vertically movable elevator mechanism;

a second, vertically movable, generally circular horizontal array of fingers interdigitated with the first fingers, the second fingers being adapted for holding a thin generally circular susceptor in a horizontal orientation;

a first, vertically movable elevator mechanism mounting the first fingers for moving the first fingers (a) upwardly to lift the wafer off the blade preparatory to lifting movement of the second fingers into a processing position and (b) downwardly to return the wafer to the blade; and

a second, vertically movable elevator mechanism mounting the second fingers for moving the second fingers (c) upwardly past the first fingers to lift the wafer therefrom and onto the susceptor and into the said processing position, and (d) downwardly for depositing the processed wafer onto the first fingers preparatory to return by the first fingers to the blade;

the bottom of said chamber comprising a quartz window;

radiant heating means mounted to the housing beneath the window and comprising a circular array of quartz-tungsten-halogen lamps and a reflector module having an annular reflecting channel therein aligned with the periphery of the horizontal susceptor, the reflector module mounting the lamps in a general vertical orientation in a circular array within the channel, for directing a substantially-collimated beam of near-IR radiant energy from the lamps through the quartz window onto the susceptor with a power density substantially higher at the edge of the susceptor than at the center thereof;

the manifold comprising a first central array of holes for dispensing deposition gas, and further comprising a second peripheral array of holes for directing purging gas downward to the periphery of the wafer; the first and second arrays of holes each comprising a number of generally concentric rings with the first central array having random hole spacing within each ring for controlling the number of radially aligned holes; and the second peripheral array having an approximately equal number of holes in each ring arranged in a radially staggered pattern free of ring-to-ring radial alignment of holes;

an annular second inlet manifold positioned around the bottom of the chamber adjacent the quartz window for directing purge gas into the chamber;

an annular exhaust channel defined within the housing about the periphery of the wafer deposition position;

vacuum means coupled to the annular exhaust chamber for applying a vacuum to the chamber, whereby application of the vacuum and application of purge gas to the first and second manifolds causes a first purge gas flow downwardly from the first manifold to the outer periphery of the wafer and a second purge gas flow from the second manifold sweeping across the quartz window, then upwardly past the bottom edge of the wafer, said two flows merging and flowing out of the chamber, thereby removing spent deposition gas and entrained products;

the susceptor being connected to ground; and

the reactor also comprising a deposition gas feed-through device connected to the first manifold, comprising: tube means having inlet and outlet ends and being adapted for providing co-axial flow of deposition gas on the inside thereof and purge gas on the outside thereof into the first manifold, the tube means being adapted for connection to ground at the inlet end and to an RF power supply at the outlet or manifold end, and the tube means also having a controlled electrical impedance along its length for establishing a constant voltage gradient along said length to prevent breakdown of the gas therein.

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BACKGROUND OF THE INVENTION

The present invention relates to a reactor and methods for performing single and in-situ multiple integrated circuit processing steps, including thermal CVD, plasma-enhanced chemical vapor deposition (PECVD), reactor self-cleaning, film etchback, and modification of profile or other film property by sputtering. The present invention also relates to a process for forming conformal, planar dielectric layers on integrated circuit wafers and to an in-situ multi-step process for forming conformal, planar dielectric layers that are suitable for use as interlevel dielectrics for multi-layer metallization interconnects.

I. Reactor

The early gas chemistry deposition reactors that were applied to semiconductor integrated circuit fabrication used relatively high temperature, thermally-activated chemistry to deposit from a gas onto a heated substrate. Such chemical vapor deposition of a solid onto a surface involves a heterogeneous surface reaction of gaseous species that adsorb onto the surface. The rate of film growth and the film quality depend on the wafer surface temperature and on the gaseous species available.

More recently, low temperature plasma-enhanced deposition and etching techniques have been developed for forming diverse materials, including metals such as aluminum and tungsten, dielectric films such as silicon nitride and silicon dioxide, and semiconductor films such as silicon.

The plasma used in the available plasma-enhanced chemical vapor deposition processes is a low pressure reactant gas discharge which is developed in an RF field. The plasma is, by definition, an electrically neutral ionized gas in which there are equal number densities of electrons and ions. At the relatively low pressures used in PECVD, the discharge is in the "glow" region and the electron energies can be quite high relative to heavy particle energies. The very high electron temperatures increase the density of disassociated species within the plasma which are available for deposition on nearby surfaces (such as substrates). The enhanced supply of reactive free radicals in the PECVD processes makes possible the deposition of dense, good quality films at lower temperatures and at faster deposition rates (300-400 Angstroms per minute) than are typically possible using purely thermally-activated CVD processes (100-200 Angstroms per minute). However, the deposition rates available using conventional plasma-enhanced processes are still relatively low. Presently, batch-type reactors are used in most commercial PECVD applications. The batch reactors process a relatively large number of wafers at once and, thus, provide relatively high throughput despite the low deposition rates. However, single-wafer reactors have certain advantages, such as the lack of within-batch uniformity problems, which make such reactors attractive, particularly for large, expensive wafers such as 5-8 inch diameter wafers. In addition, and quite obviously, increasing the deposition rate and throughput of such single wafer reactors would further increase their range of useful applications.

II. Thermal CVD of SiO.sub.2 ; Planarization Process

Recently, integrated circuit (IC) technology has advanced from large scale integration (LSI) to very large scale integration (VLSI) and is projected to grow to ultra-large integration (ULSI) over the next several years. This advancement in monolithic circuit integration has been made possible by improvements in the manufacturing equipment as well as in the materials and methods used in processing semiconductor wafers into IC chips. However, the incorporation into IC chips of, first, increasingly complex devices and circuits and, second, greater device densities and smaller minimum feature sizes and smaller separations, imposes increasingly stringent requirements on the basic integrated circuit fabrication steps of masking, film formation, doping and etching.

As an example of the increasing complexity, it is projected that, shortly, typical MOS (metal oxide semiconductor) memory circuits will contain two levels of metal interconnect layers, while MOS logic circuits may well use two to three metal interconnect layers and bipolar digital circuits may require three to four such layers. The increasing complexity, thickness/depth and small size of such multiple interconnect levels make it increasingly difficult to fabricate the required conformal, planar interlevel dielectric layers materials such as silicon dioxide that support and electrically isolate such metal interconnect layers.

The difficulty in forming planarized conformal coatings on small stepped surface topographies is illustrated in FIG. 16. There, a first film such as a conductor layer 171 has been formed over the existing stepped topography of a partially completed integrated circuit (not shown) and is undergoing the deposition of an interlayer dielectric layer 172 such as silicon dioxide. This is done preparatory to the formation of a second level conductor layer (not shown). Typically, where the mean-free path of the depositing active species is long compared to the step dimensions and where there is no rapid surface migration, the deposition rates at the bottom 173, the sides 174 and the top 175 of the stepped topography are proportional to the associated arrival angles. The bottom and side arrival angles are a function of and are limited by the depth and small width of the trench. Thus, for very narrow and/or deep geometries the thickness of the bottom layer 173 tends to be deposited to a lesser thickness than is the side layer 174 which, in turn, is less than the thickness of top layer 175.

Increasing the pressure used in the deposition process typically will increase the collision rate of the active species and decrease the mean-free path. This would increase the arrival angles and, thus, increase the deposition rate at the sidewalls 714 and bottom 173 of the trench or step. However, and referring to FlG 17A, this also increases the arrival angle and associated deposition rate at stepped corners 176. For steps separated by a wide trench, the resulting inwardly sloping film configuration forms cusps 177-177 at the sidewall-bottom interface. It is difficult to form conformal metal and/or dielectric layers over such topographies. As a consequence, it is necessary to separately planarize the topography.

In addition, and referring to FIG. 17B, where the steps are separated by a narrow trench, for example, in dense 256 kilobit VLSI structures, the increased deposition rate at the corner 176 encloses a void 178. Such voids are exposed by subsequent planarization procedures and may allow the second level conductor to penetrate and run along the void and short the conductors and devices along the void.

SUMMARY OF THE INVENTION

Objects

In view of the above discussion, it is one object to provide a semiconductor processing reactor which provides uniform deposition over a wide range of pressures, including very high pressures.

It is another related object to provide a versatile single wafer semiconductor processing reactor which can be used for a multiplicity of processes including thermal chemical vapor deposition, plasma-enhanced chemical vapor deposition, plasma-assisted etchback, plasma self-cleaning and sputter topography modification, either alone or in-situ in a multiple process sequence.

It is a related object to provide such a reactor which accomplishes the above objectives and also is adapted for using unstable gases such as TEOS and ozone.

It is another object of the present invention to provide a process for forming highly conformal silicon dioxide layers, even over small dimension stepped topographies in VLSI and ULSI devices, using ozone and TEOS gas chemistry and thermal CVD.

It is also an object of the present invention to provide a planarization process which provides excellent conformal coverage and eliminates cusps and voids.

It is still another object of the present invention to provide a planarization process which can be performed in-situ using a multiple number of steps, in the same plasma reactor chamber, by simply changing the associated reactant gas chemistry and operation conditions.

It is yet another object of the present invention to provide an in-situ multiple step process including plasma deposition and isotropic etching of a wafer for the purpose of optimizing coating conformality and planarization, along with process throughput and wafer characteristics such as low particulates.

Another object is to provide the above-described versatile process characteristics along with the ability to vary the process sequence and the number of steps, including but not limited to the addition of reactor self-cleaning.

SUMMARY

In one specific aspect, our invention relates to a semiconductor processing reactor defining a chamber for mounting a wafer therein and an inlet gas manifold for supplying reactant gases to the wafer. The chamber also incorporates a uniform radial pumping system which includes vacuum exhaust pump means; a gas distributor plate mounted peripherally about the wafer mounting position within the chamber and including a circular array of exhaust holes therein; and a circular channel beneath and communicating with the hole array and having at least a single point connection to the vacuum exhaust pump for flowing gases radially from the inlet manifold across the wafer and through the exhaust port. The channel is of sufficiently large volume and conductance relative to the holes to enable controlled uniform radial gas flow across the wafer to the exhaust holes, thereby promoting uniform flow and processing (etching and deposition) over a wide range of pressures, including very high pressures up to about one atmosphere.

In another aspect, the present invention is directed to a semiconductor processing reactor which comprises a housing forming a chamber for mounting a wafer horizontally, a vacuum exhaust pumping system communicating with the chamber, and an inlet gas manifold oriented horizontally over the wafer mounting position. The manifold has a central array of process gas apertures configured for dispensing reactant gas uniformly over the wafer and a second peripheral array of purging gas apertures configured for directing

In another aspect, the reactor incorporates a system for circulating fluid of controlled temperature within the manifold for maintaining the internal surfaces within a selected temperature range to prevent condensation and reactions within the manifold and for maintaining the external manifold surfaces above a selected temperature range for eliminating unwanted deposition thereon.

In still another aspect, the reactor of the present invention comprises a thin susceptor for supporting a wafer, susceptor support means for mounting the susceptor in a horizontal position precisely parallel to the gas inlet manifold and means for selectively moving the wafer support means vertically to position the susceptor and support parallel to the gas manifold at selected variable-distance positions closely adjacent the gas manifold. In particular, the variable parallel close spacing can be 0.5 centimeter and smaller.

In still another aspect, the semiconductor processing reactor of the present invention comprises a housing defining a chamber therein adapted for the gas chemistry processing of a wafer positioned within the chamber. A transparent window forms the bottom of the chamber. A thin high emissivity susceptor is used for supporting a wafer within the chamber. A radiant heating module comprising a circular array of lamps mounted in a reflector module is mounted outside the housing for directing a substantially collimated beam of near-infrared radiant energy through the window onto the susceptor with an incident power density substantially higher at the edge of the susceptor than at the center thereof, to heat the wafer uniformly.

Preferably, a second, purge gas manifold is positioned beneath the wafer processing area for providing purging gas flow across the window and upward and across the bottom of the wafer. The combination of the high pressure, the purge flow from the inlet gas manifold and that from the purge gas manifold substantially eliminates deposition on chamber surfaces.

In still another aspect, the reactor of the present invention comprises a deposition gas feed-through device connected to the gas inlet manifold which comprises tube means adapted for providing co-axial flow of deposition gas on the inside of the tube and purge gas on the outside thereof into the gas inlet manifold. The tube is adapted for connection to ground at the inlet end and to an RF power supply at the outlet or manifold end to provide RF power to the manifold, and has a controlled electrical impedance along its length from the inlet to the outlet end for establishing a constant voltage gradient to prevent breakdown of the gas even at high RF frequencies and voltages.

These and other features discussed below permit reactor operation over a wide pressure regime, that is, over a wide of pressures including high pressures up to approximately one atmosphere. The features also provide uniform susceptor and wafer temperatures, including both absolute temperature uniformity and spatial uniformity across the susceptor/wafer; uniform gas flow distribution across the wafer; and effective purging. The variable parallel close spacing between the electrodes adapts the reactor to various processes. These features and the temperature control of the internal and external gas manifold temperatures enable the advantageous use of very sensitive unstable gases such as ozone and TEOS in processes such as the following.

That is, the present invention also relates to a method for depositing a conformal layer of silicon dioxide onto a substrate by exposing the substrate to a reactive species formed from ozone, oxygen, tetraethylorthosilicate, and a carrier gas within a vacuum chamber, using a total gas pressure within the chamber 10 torr to 200 torr and a substrate temperature within the range of about 200.degree. C. to 500.degree. C. Preferably, a substrate temperature of about 375.degree. C. .+-.20.degree. C. is used to obtain maximum deposition rates and the chamber pressure is about 40 torr to 120 torr.

In still another aspect, the present invention is embodied in a method for depositing silicon dioxide onto a film or substrate by exposing the substrate to the plasma formed from tetraethylorthosilicate, oxygen and a carrier gas in a chamber using a total gas pressure within the range of about 1 to 50 torr, and a substrate temperature in the range of about 200.degree. C. to 500.degree. C. Preferably, the chamber pressure is 8-12 torr and the substrate temperature is about 375.degree. C. .+-.20.degree. C.

In still another aspect, the invention is directed to a method for isotropically etching a silicon dioxide surface comprising the step of exposing a silicon dioxide surface to a plasma formed from fluorinate gas such as NF.sub.3, CF.sub.4 and C.sub.2 F.sub.6 in a carrier gas in a chamber using a wafer temperature in the range of from about 200.degree. C. to 500.degree. C. Preferably, the chamber pressure is within the range of about 200 mT to 20 torr and 500 mT to 10 torr.

The invention is also embodied in a method for planarizing a non-planar dielectric coating or composite within a vacuum chamber by depositing a conformal layer of silicon dioxide onto the coating by exposing the coating to a reactive species formed from ozone, oxygen, tetraethylorthosilicate and a carrier gas, the total chamber gas pressure being within the approximate range 10 torr to 200 torr and the substrate temperature being within the approximate range 200.degree. C. to 500.degree. C., to thereby form a composite of the conformal layer on the substrate; and isotropically etching the outer surface of the resulting composite layer. Preferably, this planarizing process uses the plasma oxide deposition to first form a layer of silicon oxide and also uses the isotropic etch described above.

BRIEF DESCRI