In a microprogram-controlled device operable under the control of a microprogram, a control storage device (10) comprises a control storage unit (11) memorizing a plurality of microinstructions each including a plurality of every second microinstruction addresses in number less than the maximum number of available branches for the microprogram. A bank switching unit (12) selects, as a selected microinstruction (SMI), one of the next microinstructions on the basis of a branch information signal (BI). A microinstruction register (13) holds the selected microinstruction as a current microinstruction. A branch control unit (15) processes a branch condition signal (BCD), a branch control signal (BCT), a branch classification signal (BCF), and a branch condition selection signal (BCS) into the branch information signal, an address selection signal (AS), and an address modifying signal (AM). An address selector (16) selects, as a selected microinstruction address (SMIA), one of the every second microinstruction addresses on the basis of the address selection signal. An address modifier (17) modifies the selected microinstruction address into a modified microinstruction address (MMIA) on the basis of the address modifying signal and an address modifying selection signal (AMS). The address modifier supplies an address register (14) with the modified microinstruction address.

Disclosed is a system for improved instruction fetch prediction. When a jump instruction is encountered, the preceding instruction is considered in predicting the next instruction to fetch. If the preceding instruction is a skip instruction, the result of evaluating a condition specified by the skip instruction is used in predicting the next instruction to fetch. Prediction designators for skip/jump sequences of instructions are maintained in a jump prediction RAM.

A signal which requires an interruption of execution of program instructions stored in a memory, is produced. The program instructions include an entry point instruction at an entry point to which a branch instruction transfers control. An instruction decoder is operatively coupled to the memory and receives the program instructions in sequence. A preceding branch instruction is coupled to the decoder and is arranged to store a signal which is applied from the decoder and which indicates whether or not the program instruction decoded by the decoder is a branch instruction. The instruction decoder further receives the signal from the indicator. The instruction decoder produces the first mentioned signal when receiving the entry point instruction which indicates that control has been transferred to a new program flow, if the signal indicates that the program instruction decoded by the decoder is not a branch instruction.

A computer program product, method and apparatus for utilizing common prefix codes in computing instructions so as to reduce the number instructions required to perform identical operations for varying operand sizes. In one form, the common prefix code is appended as the higher order portion of the instruction word to form a second series of instructions. These computing instructions may be utilized in conjunction with a flag register, which, in one application, designates which series of instructions to use; either the original instructions or the modified instructions containing the common prefix. In another application, the flag register designates which register or memory should be used to store the operands and the associated results. Through the use of common prefix codes and the flag register, operands of various sizes can be efficiently manipulated through a simplified scheme of instructions.

This invention performs conditional operations and conditional branches based upon mixed conditions. The invention performs a first arithmetic/logical operation via an arithmetic logic unit (230). At least one status bit in a status register (210) is set based upon the results. This status bit could be a negative status bit, a carry out status bit, an overflow status bit or a zero status bit. In a first embodiment, the arithmetic logic unit (230) performs a second operation conditional upon a selected one of the status bits. The status bits are then set based upon the results of this second operation. A third operation, which could be an arithmetic logic unit operation, a memory load, memory store, a register to register move, a subroutine call, subroutine return or program branch, is conditional upon the selected status bit, thus performing upon the logical AND of the results of the first and second operations. In a second embodiment, the second operation is conditioned on the inverse of the selected status bit. The result of this second operation also sets the status bits. The third operation is conditional upon the selected status bit. Thus the third operation is performed if either the first operation or the second operation sets the selected status bit forming a logical OR of the results of the first and second operations.