A direct digital synthesizer that outputs at least a predetermined output frequency related signal from a received digital signal, K, with minimum spurious signal levels. A storage device stores an initial phase value of the digital signal, K, and provides the initial phase value on an output thereof. An adder is provided having a first input for receiving the digital signal, K, having a second input and having an output which provides a summation of signals received on the first and second inputs. A latch has a first input connected to the output of the storage device, has a second input connected to the output of the adder and an output connected to the second input of the adder. The latch also has a third input for receiving a select signal for selecting between receiving on the first and second inputs of the latch. A control circuit provides the select signal in response to one of a plurality of predetermined parameters. The output frequency related signal is provided on the output of the latch. One or more detectors identify a power interrupt of the direct digital synthesizer or a change in the digital signal, K, and provides a detect signal to the control circuit. When a power interrupt or change in K is detected, the control circuit causes the latch to first receive the initial phase value on the first input thereof and then switch to the second input thereof for subsequent operations.
Spurious frequency components from the output signal of a direct digital synthesizer are reduced with minimum degradation of the fundamental frequency of the output signal. The synthesizer has a phase accumulator for receiving digital multibit modulation data words from a source, a periodic wave function converter for converting the modulation data words into digital waveform data words and a digital-to-analog converter for converting the digital waveform data words into an analog signal which serves as the output signal. The output signal has a frequency and waveform dictated by the modulation data words. Reduction of spurious frequency components is achieved by generating a dither waveform representing a band limited waveform. The dither waveform is summed with the modulation data words prior to application to the wave function converter to provide a dither modulated analog output signal. A sampled dither signal is combined with the dither modulated analog output signal in such a manner that the dither waveform is cancelled from the fundamental waveform of the analog output signal.
A direct digital synthesizer (DDS) for generating an output periodic waveform from a stored digital waveform has a linear feedback shift register coonfigured as a counter. The linear feedback shift register is clocked by the internal reference clock of the DDS, and a predetermined output of the linear feedback shift register is detected to provide a control signal. The control signal causes the frequency or phase of the output waveform to be changed according to control parameters input to a control logic circuit. The control logic circuit preloads the new parameter vlaues into appropriate frequency/phase registers which are switched to the input of the accumulator in the DDS on the next cycle of the reference clock when the control signal is detected.
Methods and apparatus for variable-rate down-sampling filters for discrete-time sampled systems using a fixed sampling rate are disclosed. The Variable Rate Down-Sampling Filter allows a continuous range of sample rates to be derived from input samples at a fixed rate. The output rate does not have to be related to the fixed input rate in any integral or rational way, and in fact, the output rate can vary in time such as will occur when tracking a signal received from a station using a different timebase. A fixed sampling rate at the A/D Converter greatly simplifies the design of the analog front end. A single anti-aliasing filter can be designed and precisely matched to the fixed sampling rate. Used with a frequency-modulated numerically controlled oscillator (NCO), the Down-Sampling Filter keeps the entire frequency-synthesis and time-tracking loop in the digital domain. The need for an analog time-tracking loop to adjust the sampling instant at the A/D converter is eliminated. The need for an analog frequency synthesizer to generate a variable sampling rate is also eliminated. System design and performance analysis are simplified as well by eliminating the complication of hybrid analog-digital control loops. Details are disclosed.
A direct digital synthesizer of the phase-accumulator type, constructed entirely of binary-radix digital hardware, generates signals with decimally-defined frequency resolution. The synthesizer is supplied with a clock signal which is also decimally-defined. The usual decimal-binary incompatibility problems of such a combination are overcome by the use of a phase accumulator which is partitioned into two segments. The first segment is assigned the most significant portion of the desired frequency, and the other segment is assigned the remaining portion of the desired frequency. The two segments have different arithmetic moduli. Typically, the modulus of the first segment is a power of two, while that of the second segment is an integer other than a power of two. A procedure is given for determining both the point of partition and the second arithmetic modulus.
A digital oscillator including an integrator for cumulatively integrating a specified signal and a controller responsive to a control signal for maintaining the output frequency of the integrator within a limit corresponding to the amplitude of the control signal.
