Methods and apparatus for providing pixel brightness correction in monitors. The methods and apparatus disclosed herein provide significant cost reductions in gamma correction circuitry by first degamma correcting pixel value data stored on a frame buffer, and then gamma correcting the degamma corrected pixel value data before the data is stored back on the frame buffer. Circuits for providing pixel brightness correction in a monitor comprise logic circuits for generating upper bits of a data word representing pixel intensity, shifter circuits interfaced with the logic circuits for generating lower bits of the data word representing pixel intensity, and combining circuits interfaced with the logic circuits and the shifter circuits for generating intermediate bits of the data word representing pixel intensity.
A gamma correction circuit in which digitized video intensity values are divided into high and low intensity ranges. Every fourth high value is gamma corrected in a lookup table and written to a frame buffer. All of the low intensity values are written to the buffer without gamma correction. The data in the buffer is mapped by a second lookup table before being converted to an analog signal. The second table maps the low intensity values to gamma corrected values and does not change the value of the high intensity values. When data is read from the frame buffer for further processing before display on a CRT, the lower intensity values need not be inverse gamma corrected. The high intensity values are inverse gamma corrected via a lookup table before such further processing.
A method and circuit for improving a video signal. They can be used to nullify the gamma correction applied at the broadcast end for cathode-ray tube signals when using a spatial light modulator display. Additionally, the method and circuit can be used to generally improve the quality of the display for computer monitors or other formats that do not require the gamma nullification.
A non-linear digital video compression circuit and method. The video compression circuit includes a source of digital video data signal, wherein the digital video data has M-bits of information for each of a Y, U, and V value per pixel. Y represents a luminance component, and U and V each represent portions of a two-dimensional chromaticity component. The circuit also includes a compression lookup table having an M-bit input coupled to the source of digital video data, and an N-bit compressed digital video data output, where N is less than M. The compression lookup table includes a non-linear compression transformation for at least one of Y, U and V. In one embodiment, the compression lookup table includes a non-linear compression transformation that provides a different conversion for Y than for U or that provides a different conversion for Y than for V. In one such embodiment, the digital video compression circuit further includes a Y-U-V state circuit coupled to the compression lookup table that controls which one of the conversions for Y and U and V is performed. In one such embodiment, M is ten and N is eight (thus providing a 10-bit to 8-bit compression), and the state circuit has an output coupled to the compression lookup table that specifies which one of the conversions is performed.
An error correction method and circuit for a nonlinear quantization circuit comparing a test signal which is produced from an error correction table by applying an analog reference signal into a nonlinear circuit with reference data that is defined as an output of the error correction table when the nonlinear circuit has no error, and updating the error correction table by the test signal and the reference data when they disagree. The output of the nonlinear circuit is corrected by using the error correction table. The technique is particularly suitable for nonlinear conversion performed by a gamma correction circuit of a color television camera.
Pixel arithmetic and logical units for rendering pixels in graphics systems. Circuits for performing arithmetic operations on raster scan data are provided. The circuits comprise opcode registers for selecting an arithmetic function which transforms pixel value data corresponding to graphics primitives, multiplication circuits interfaced with the opcode registers for multiplying graphics operators with graphics data to obtain transform pixel value data, combining circuits interfaced with the multiplication circuits for adding transform pixel value data to existing pixel value data and processing circuitry interfaced with the combining circuitry for storing overflow data from the combining circuitry when adding transform pixel data overflows the combining circuitry.